ISL6263CHRZ datasheet(13/18 Pages) RENESAS

13 / 18 page

ISL6263C

FN6745 Rev 1.00

Page 13 of 18

July 8, 2010

an external capacitor across the BOOT and PHASE pins

completes the bootstrap circuit.

The minimum value of the bootstrap capacitor can be calculated

using Equation 3:

where QGATE is the amount of gate charge required to fully

charge the gate of the upper MOSFET. The

VBOOT term is

defined as the allowable droop in the rail of the upper drive.

As an example, suppose an upper MOSFET has a gate

charge, QGATE, of 25nC at 5V and also assume the droop in

the drive voltage at the end of a PWM cycle is 200mV. One will

find that a bootstrap capacitance of at least 0.125µF is

required. The next larger standard value capacitance is

0.15µF. A good quality ceramic capacitor is recommended.

Soft-Start and Soft Dynamic VID Slew Rates

The output voltage of the converter tracks VSOFT, the voltage

across the SOFT and VSS pins. Shown in Figure 1, the SOFT

pin is connected to the output of the VID DAC through the

unidirectional soft-start current source ISS or the bidirectional

soft-dynamic VID current source IDVID, and the non-inverting

input of the error amplifier. Current is sourced from the SOFT

pin when ISS is active. The SOFT pin can both source and sink

current when IDVID is active. The soft-start capacitor CSOFT

changes voltage at a rate proportional to ISS or IDVID. The

ISL6263C automatically selects ISS for the soft-start sequence

so that the inrush current through the output capacitors is

maintained below the OCP threshold. Once soft-start has

completed, IDVID is automatically selected for output voltage

changes commanded by the VID inputs, charging CSOFT when

the output voltage is commanded to rise, and discharging

CSOFT when the output voltage is commanded to fall.

The GPU voltage regulator may require a minimum voltage

slew rate, which will be guaranteed by the value of CSOFT. For

example, if the regulator requires 10mV/µs slew rate, the value

of CSOFT can be calculated using Equation 4:

IDVID is the soft-dynamic VID current source, and its minimum

value is specified in the “Electrical Specifications” table on

page 5. Choosing the next lower standard component value of

0.015µF will guarantee 10mV/µs slew rate. This choice of

CSOFT controls the startup slew-rate as well. One should

expect the output voltage during soft-start to slew to the

voltage commanded by the VID settings at a nominal rate

given by Equation 5:

Note that the slew rate is the average rate of change between

the initial and final voltage values.

It is worth it to mention that the surge current charges the

output capacitors when the output voltage is commanded to

rise. This surge current could be high enough to trigger the OC

protection circuit if the voltage slew rate is too high, or/and the

output capacitance is too large. The overcurrent set point

should guarantee the VID code transition successful.

RBIAS Current Reference

The RBIAS pin is internally connected to a 1.545V reference

through a 3kΩ resistance. A bias current is established by

connecting a

±1% tolerance, 150kΩ resistor between the RBIAS

and VSS pins. This bias current is mirrored, creating the reference

current IOCSET that is sourced from the OCSET pin. Do not

connect any other components to this pin, as they will have a

negative impact on the performance of the IC.

Setting the PWM Switching Frequency

The R3 modulator scheme is not a fixed-frequency

architecture, lacking a fixed-frequency clock signal to produce

PWM. The switching frequency increases during the

application of a load to improve transient performance. The

static PWM frequency varies slightly depending on the input

voltage, output voltage, and output current, but this variation is

normally less than 10% in continuous conduction mode.

Refer to Figure 2 and find that resistor RFSET is connected

between the V W and COMP pins. A current is sourced from VW

through RFSET creating the synthetic ripple window voltage

signal VW, which determines the PWM switching frequency. The

relationship between the resistance of RFSET and the switching

frequency in CCM is approximated using Equation 6:

t is the switching period. For example, the value of RFSET for

300kHz operation is approximated using Equation 7:

FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

20nC

VBOOT_CAP (V)

2.0

1.6

1.4

1.0

0.8

0.6

0.4

0.2

0.0

0.3

0.0

0.1

0.2

0.4

0.5

0.6

0.9

0.7

0.8

1.0

QGATE = 100nC

1.2

1.8

CBOOT

QGATE

V

BOOT

------------------------



(EQ. 3)

CSOFT

IDVIDmin

10mV

s

----------------





-------------------------

180

A

10K

------------------

0.018

F

(EQ. 4)

dVSOFT

-----------------------

ISS

CSOFT

-------------------

A

0.015

F

-----------------------

2.8mV

s

------------------



(EQ. 5)

RFSET

t0.5 10

–



–



400 10

–



---------------------------------------

(EQ. 6)

ISL6263CHRZ bảng dữ liệu(PDF) 13 Page - Renesas Technology Corp

ISL6263CHRZ bảng dữ liệu(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

bảng dữ liệu tải về

Link URL