TUSB1044 datasheet(36/67 Pages) TI1

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TUSB1044

SLLSF47B – FEBRUARY 2018 – REVISED APRIL 2018

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7.6 Register Maps

7.6.1 TUSB1044 Registers

Table 10 lists the memory-mapped registers for the TUSB1044. All register offset addresses not listed in

Table 10 should be considered as reserved locations and the register contents should not be modified.

Table 10. TUSB1044 Registers

Offset

Acronym

Section

General_1

General Registers 1

General_2

General Registers 2

General_3

General Registers 3

10h

UFP2_EQ

UFP2 EQ Control

11h

UFP1_EQ

UFP1 EQ Control

12h

DisplayPort_1

AUX Snoop Status

13h

DisplayPort_2

DP Lane Enable/Disable Control

1Bh

SOFT_RESET

I2C and DPCD Soft Resets

20h

DFP2_EQ

DFP2 EQ Control

21h

DFP1_EQ

DFP1 EQ Control

22h

USB3_MISC

Misc USB3 Controls

23h

USB3_LOS

USB3 LOS Threshold Controls

Complex bit access types are encoded to fit into small table cells. Table 11 shows the codes that are used for

access types in this section.

Table 11. TUSB1044 Access Type Codes

Access Type

Code

Description

Read Type

Read

Set or cleared by hardware

Read

Write Type

Set or cleared by hardware

Write

WSH

Set or cleared by hardware

Write

Reset or Default Value

-n

Value after reset or the default value

i,j,k,l,m,n

When these variables are used in a register name,

an offset, or an address, they refer to the value of a

of repeating registers. The register groups form a

hierarchical structure and the array is represented

with a formula.

When this variable is used in a register name, an

offset, or an address it refers to the value of a

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