HIP6004B datasheet(8/15 Pages) RENESAS

8 / 15 page

HIP6004B

FN4567 Rev 3.00

Page 8 of 15

November 9, 2004

Figure 5 shows the critical power components of the converter. To

minimize the voltage overshoot the interconnecting wires

indicated by heavy lines should be part of ground or power plane

in a printed circuit board. The components shown in Figure 5

should be located as close together as possible. Please note that

the capacitors CIN and CO each represent numerous physical

capacitors. Locate the HIP6004B within 3 inches of the

MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate

and source connections from the HIP6004B must be sized to

handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional layout

consideration. Use single point and ground plane construction

for the circuits shown. Minimize any leakage current paths on

the SS PIN and locate the capacitor, CSS close to the SS pin

because the internal current source is only 10µA. Provide local

VCC decoupling between VCC and GND pins. Locate the

capacitor, CBOOT as close as practical to the BOOT and

PHASE pins.

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(VOUT) is regulated to the Reference voltage level. The error

amplifier (Error Amp) output (VE/A) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width

modulated (PWM) wave with an amplitude of VIN at the

PHASE node.

TABLE 1. OUTPUT VOLTAGE PROGRAM

PIN NAME

NOMINAL OUTPUT

VOLTAGE DACOUT

PIN NAME

NOMINAL OUTPUT

VOLTAGE DACOUT

VID4

VID3

VID2

VID1

VID0

VID4

VID3

VID2

VID1

VID0

111

1.30

111

110

1.35

111

2.1

101

1.40

110

2.2

100

1.45

110

2.3

011

1.50

101

2.4

010

1.55

101

2.5

001

1.60

100

2.6

000

1.65

100

2.7

111

1.70

011

2.8

110

1.75

011

2.9

101

1.80

010

3.0

100

1.85

010

3.1

011

1.90

001

3.2

010

1.95

001

3.3

001

2.00

000

3.4

000

2.05

000

3.5

NOTE: 0 = connected to GND or VSS, 1 = connected to VDD through pull-up resistors.

PGND

LGATE

UGATE

PHASE

VIN

VOUT

RETURN

HIP6004B

CIN

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+12V

HIP6004B

GND

VCC

BOOT

VOUT

PHASE

+VIN

CBOOT

CVCC

CSS

HIP6004B

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