XRT83SL38IV datasheet(21/89 Pages) EXAR

21 / 89 page

XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.1.0

EQC4

EQC3

EQC2

EQC1

EQC0

RDY_DTACK

ALE_AS

RD_DS

WR_R/W

194

193

192

191

190

194

193

192

191

190

Equalizer Control Input 4 - Hardware mode

This pin together with pins EQC[3:0] is used to control the transmit pulse

shaping, transmit line build-out (LBO) and receive monitoring while operating

at one of either the T1, E1 or J1 clock rates/modes. See “Receive Equalizer

Control and Transmit Line Build-Out Settings” on page 29. for description of

Transmit Equalizer Control bits.

Equalizer Control Input 3

Equalizer Control Input 2

Equalizer Control Input 1

Equalizer Control Input 0

NOTES:

In Hardware mode all transmit channels share the same pulse

setting controls function.

All channels of an XRT83L38 must operate at the same clock rate,

either the T1, E1 or J1 modes.

In Host mode, these pins perform various microprocessor functions. See

“Microprocessor Interface” on page 11.

NOTE: Internally pulled “Low” with a 50k

Ω resistor.

RXTSEL

U11

Receiver Termination Select

In Hardware mode, when this pin is “Low” the receive line termination is

determined only by an external resistor. When “High”, the receive termination

is realized by the internal resistor or the combination of internal and external

resistors. These conditions are described in the table below.

NOTE: In Hardware mode all channels share the same RXTSEL control

function.

In Host mode, the RXTSEL_n bits in the channel control registers determine

if the receiver termination is external or internal. However, the function of RXT-

SEL can be transferred to the Hardware pin by setting the TERCNTL bit (bit

6) to “1” in the register address hex 0x82.

NOTE: This pin is internally pulled “Low” with a 50k

Ω resistor.

SIGNAL NAME

TQFP

PIN #

BGA

LEAD #

TYPE

DESCRIPTION

RXTSEL

RX Termination

External

Internal

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