HIP6521

FN4837 Rev.5.00

Page 9 of 13

Oct 16, 2006

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

a closed loop transfer function with high 0dB crossing

180°. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 6. Use these guidelines for

locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Compensation Break Frequency Equations

Figure 7 shows an asymptotic plot of the DC/DC converter’s

gain vs. frequency. The actual Modulator Gain has a high

gain peak dependent on the quality factor (Q) of the output

filter, which is not shown in Figure 6. Using the above

guidelines should yield a Compensation Gain similar to the

curve plotted. The open loop error amplifier gain bounds the

with the capabilities of the error amplifier. The Closed Loop

Gain is constructed on the log-log graph of Figure 10 by

adding the Modulator Gain (in dB) to the Compensation Gain

(in dB). This is equivalent to multiplying the modulator

transfer function to the compensation transfer function and

plotting the gain.

The compensation gain uses external impedance networks

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin.

ACPI Implementation

The three linear controllers included within the HIP6521 can

independently be shut down, in order to accommodate

Advanced Configuration and Power Interface (ACPI) power

management features.

To shut down any of the linears, one needs to pull and keep

high the respective FB pin above a typical threshold of

1.25V. One way to achieve this task is by using a logic gate

coupled through a small-signal diode. The diode should be

placed as close to the FB pin as possible to minimize stray

capacitance to this pin. Upon turn-off of the pull-up device,

the respective output undergoes a soft-start cycle, bringing

the output within regulation limits. On the regulators

implementing this feature, the parallel combination of the

feedback resistors has to be sufficiently high to allow ease of

driving from the external device. Considering the other

restriction applying to the upper range of this resistor

combination (see ‘Output Voltage Selection’ paragraph), it is

recommended the values of the feedback resistors on an

ACPI-enabled linear regulator output meet the following

constraint:

To turn off the switching regulator, use an open-drain or

open-collector device capable of pulling the OCSET pin (with

possibility of OC trips at levels different than predicted, a

larger than the output capacitance of the pull-down device,

Upon turn-off of the pull-down device, the switching regulator

undergoes a soft-start cycle.

1

2







----------------------------------------

=

1

2

 ESR C

O





-----------------------------------------

=

1

2

 R

 2C1



-----------------------------------

=

1

2



+

 C3





----------------------------------------------------------

=

1

2

 R

2

C1 C2



C1 C2

+

----------------------









-------------------------------------------------------

=

1

2

 R

 3C3



-----------------------------------

=

FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

100

80

60

40

20

0

-20

-40

-60

10M

1M

100K

10K

1K

100

10

OPEN LOOP

ERROR AMP GAIN

COMPENSATION

FREQUENCY (Hz)

GAIN

MODULATOR

GAIN

CLOSED LOOP

GAIN

20

VIN

VPP

------------







log

20

R2

-------------







log

2k





+

---------------------- 5k



