HIP6311CB datasheet(9/17 Pages) RENESAS

9 / 17 page

HIP6311

FN4817 Rev 3.00

Page 9 of 17

December 27, 2004

Figure 3 shows the start-up sequence as initiated by a fast

rising 5V supply, VCC, applied to the HIP6311. Note the short

rise to the three state level in PWM 1 output during first 32

PWM cycles.

Figure 4 shows the waveforms when the regulator is

operating at 200kHz. Note that the Soft-Start duration is a

function of the Channel Frequency as explained previously.

Also note the pulses on the COMP terminal. These pulses

are the current correction signal feeding into the comparator

input (see the Block Diagram on page 2.)

Figure 5 shows the regulator operating from an ATX supply.

In this figure, note the slight rise in PGOOD as the 5V supply

rises.The PGOOD output stage is made up of NMOS and

PMOS transistors. On the rising VCC, the PMOS device

becomes active slightly before the NMOS transistor pulls

“down”, generating the slight rise in the PGOOD voltage.

Note that Figure 5 shows the 12V gate driver voltage

available before the 5V supply to the HIP6311 has reached

its threshold level. If conditions were reversed and the 5V

supply was to rise first, the start-up sequence would be

different. In this case the HIP6303 will sense an over-current

condition due to charging the output capacitors. The supply

will then restart and go through the normal Soft-Start cycle.

Fault Protection

The HIP6311 protects the microprocessor and the entire

power system from damaging stress levels. Within the

HIP6311 both Over-Voltage and Over-Current circuits are

incorporated to protect the load and regulator.

Over-Voltage

The VSEN pin is connected to the microprocessor CORE

voltage. A CORE over-voltage condition is detected when

the VSEN pin goes more than 15% above the programmed

VID level.

The over-voltage condition is latched, disabling normal PWM

operation, and causing PGOOD to go low. The latch can

only be reset by lowering and returning VCC high to initiate a

POR and Soft-Start sequence.

During a latched over-voltage, the PWM outputs will be

driven either low or three state, depending upon the VSEN

input. PWM outputs are driven low when the VSEN pin

detects that the CORE voltage is 15% above the

programmed VID level. This condition drives the PWM

outputs low, resulting in the lower or synchronous rectifier

MOSFETS to conduct and shunt the CORE voltage to

ground to protect the load.

If after this event, the CORE voltage falls below the over-

voltage limit (plus some hysteresis), the PWM outputs will

three state. The HIP6601 family drivers pass the three state

information along, and shuts off both upper and lower

MOSFETs. This prevents “dumping” of the output capacitors

PWM 1

PGOOD

VCORE

OUTPUT

VCC

VIN = 12V

DELAY TIME

FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT

500kHz

PGOOD

VCORE

V COMP

VCC

VIN = 12V

DELAY TIME

FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT

200kHz

12V ATX

SUPPLY

PGOOD

5 V ATX

VCORE

SUPPLY

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

VIN = 5V, CORE LOAD CURRENT = 31A

FIGURE 5. SUPPLY POWERED BY ATX SUPPLY

FREQUENCY 200kHz

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