HIP6311 datasheet(13/17 Pages) RENESAS

13 / 17 page

HIP6311

FN4817 Rev 3.00

Page 13 of 17

December 27, 2004

average current per phase. Neglecting secondary effects,

the sampled current (ISAMPLE) can be related to the load

current (ILT) by:

ISAMPLE = ILT / n + (VINVCORE - 3VCORE2) / (6L x FSW x

VIN)

Where: ILT = total load current

n = the number of channels

Example: Using the previously given conditions, and

For ILT = 100A,

n= 4

Then ISAMPLE = 25.49A

As discussed previously, the voltage drop across each Q2

transistor at the point in time when current is sampled is

rDSON (Q2) x ISAMPLE. The voltage at Q2’s drain, the

PHASE node, is applied through the RISEN resistor to the

HIP6311 ISEN pin. This pin is held at virtual ground, so the

current into ISEN is:

ISENSE = ISAMPLE x rDS(ON) (Q2) / RISEN.

RIsen

= ISAMPLE x rDS(ON) (Q2) / 50A

Example: From the previous conditions,

where ILT

= 100A,

ISAMPLE

= 25.49A,

rDS(ON) (Q2)

= 4m



Then: RISEN

= 2.04K and

ICURRENT TRIP = 165%

Short circuit ILT = 165A.

Channel Frequency Oscillator

The channel oscillator frequency is set by placing a resistor,

RT, to ground from the FS/DIS pin. Figure 10 is a curve

showing the relationship between frequency, FSW, and

resistor RT. To avoid pickup by the FS/DIS pin, it is important

to place this resistor next to the pin. If this pin is also used to

disable the converter, it is also important to locate the pull-

down device next to this pin.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit

and lead to device over-voltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turnoff

transition of the upper PWM MOSFET. Prior to turnoff, the

upper MOSFET was carrying channel current. During the

turnoff, current stops flowing in the upper MOSFET and is

picked up by the lower MOSFET. Any inductance in the

switched current path generates a large voltage spike during

the switching interval. Careful component selection, tight

layout of the critical components, and short, wide circuit

traces minimize the magnitude of voltage spikes. Contact

Intersil for evaluation board drawings of the component

placement and printed circuit board.

There are two sets of critical components in a DC-DC

converter using a HIP6311 controller and a HIP6601 gate

driver. The power components are the most critical because

they switch large amounts of energy. Next are small signal

components that connect to sensitive nodes or supply critical

bypassing current and signal coupling.

The power components should be placed first. Locate the

input capacitors close to the power switches. Minimize the

length of the connections between the input capacitors, CIN,

and the power switches. Locate the output inductors and

output capacitors between the MOSFETs and the load.

Locate the gate driver close to the MOSFETs.

100

200

500 1,000

5,000 10,000

2,000

100

200

500

1,000

CHANNEL OSCILLATOR FREQUENCY, FSW (kHz)

FIGURE 10. RESISTANCE RT vs FREQUENCY

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