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STQ2HNK60ZR-AP bảng dữ liệu(PDF) 3 Page - STMicroelectronics |
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STQ2HNK60ZR-AP bảng dữ liệu(HTML) 3 Page - STMicroelectronics |
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3 / 12 page ![]() 3/12 STQ2HNK60ZR-AP - STF2HNK60Z - STD2HNK60Z-1 ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF DYNAMIC SOURCE DRAIN DIODE Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID =1mA,VGS = 0 600 V IDSS Zero Gate Voltage Drain Current (VGS =0) VDS =Max Rating VDS =Max Rating,TC = 125 °C 1 50 µA µA IGSS Gate-body Leakage Current (VDS =0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS =VGS,ID =50 µA 3 3.75 4.5 V RDS(on) Static Drain-source On Resistance VGS =10V, ID = 1.0 A 4.4 4.8 Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance VDS =15V, ID = 1.0 A 1.5 S Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V,f= 1MHz,VGS = 0 280 38 7 pF pF pF Coss eq. (3) Equivalent Output Capacitance VGS =0V, VDS = 0V to 480V 30 pF td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time VDD =300 V, ID =1.0 A RG =4.7Ω VGS =10 V (Resistive Load see, Figure 3) 10 30 23 50 ns ns ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD =480V, ID =2.0 A, VGS =10V 11 2.25 6 15 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) 2.0 8.0 A A VSD (1) ForwardOnVoltage ISD =2.0 A, VGS =0 1.6 V trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 2.0 A, di/dt = 100 A/µs VDD =20 V,Tj =25°C (see test circuit, Figure 5) 178 445 5 ns nC A trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD =13A,di/dt =100 A/µs VDD =20 V,Tj = 150°C (see test circuit, Figure 5) 200 500 5 ns nC A |
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