ISL8270MEVAL1Z datasheet(5/56 Pages) RENESAS

5 / 56 page

ISL8270M

FN8635 Rev.4.00

Page 5 of 56

Aug 17, 2017

VSWH

PWR

Switch node. Refer to the “PCB Layout Guidelines” on page 20 for connecting VSWH pads to the electrically

isolated PCB copper island to dissipate internal heat.

VOUT

PWR

Power supply output. Range: 0.6V to 5V. Refer to “Derating Curves” on page 12 for maximum recommended

output current at various output voltages.

15, 27, 40

SGND

PWR

Controller Signal ground. Refer to the “PCB Layout Guidelines” on page 20 for the SGND pad connections.

VDD

PWR

Input supply to digital controller. Connect VDD pad to VIN supply. Refer to the “PCB Layout Guidelines” on page 20

for the decoupling capacitors placement from VDD to SGND.

External enable input. Logic high enables the module.

SCL

Serial clock input. A pull-up resistor is required for this application.

SDA

I/O

Serial data. A pull-up resistor is required for this application.

SALRT

Serial alert. A pull-up resistor is required for this application.

Serial bus address select pin. Refer to Table 7 for a list of resistor values to set various serial bus addresses.

MGN

External VOUT margin control pin. Active high (>2V) signal at this pin sets VOUT margin high, Active low (<0.8V) sets

VOUT margin low and high impedance (float) will bring VOUT back to nominal voltage. The factory default range for

margining is nominal VOUT ±5%. When using PMBus to control margin command, leave this pin as no connect.

VSET

Output voltage selection pin. Refer to Table 4 for a list of resistor values to set various output voltages.

Power-Good output. Power-good output can be an open drain that requires a pull-up resistor or push-pull output

that can drive a logic input.

UVLO

VDD undervoltage lockout selection. Refer to Table 6 for a list of resistor values to set various UVLO levels.

PHASE

PWR

Switch node pad for DCR sensing. Electrically shorted inside to VSWH, but for higher current sensing accuracy

connect PHASE pad to VSWH pad externally. Refer to the “PCB Layout Guidelines” on page 20.

VR6

PWR

6V internal reference supply voltage.

VR5

PWR

5V internal reference supply voltage.

VDDC

PWR

VDD Clean. Noise at the VDD pin is filtered with ferrite bead and capacitor. For VDD > 6V, leave this pin as no

connect. For 5.5

 VDD  6V, connect VDDC pin to VR6 pin. For 4.5  VDD < 5.5V, connect VDDC pin to VR6 and

VR5 pin.

V25

PWR

2.5V internal reference supply voltage.

SYNC

I/O

SYNC pin can be input to external clock for frequency synchronization or output to supply clock signal to other

modules for synchronization. Refer to Table 5 for list of resistor values to program various switching frequencies.

4, 5, 22,

26, 32, 33

These are test pins and are not electrically isolated. Leave these pins as no connect.

Pin Descriptions (Continued)

LABEL

TYPE

DESCRIPTION

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