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Reference:CMV300-datasheet-v2.10

CMV300 Datasheet

Page 38 of 55

Offset

Default value

Description of the value

Offset_bot

Offset_top

59-60[3:0]

97-98[3:0]

The value in this register defines the dark level offset

applied to the output signal (min = 0, max = 4095)

The value must be seen as a two’s complement where

values higher than 2047 are used to give a negative offset.

Example:

- 000000000101 = 5 will add 5DN to the signal

- 111111111011 = -5 will subtract 5DN from the signal

Both offsets don’t have to be the same value.

5.13.2 GAIN

An analog gain and ADC gain can be applied to the output signal. The analog gain is applied by a PGA in every column.

The digital gain is applied by the ADC.

Gain

Default value

Description of the value

PGA_gain

80[2:0]

0: x1 gain

1: x1.25 gain

2: x1.5 gain

3: x1.75 gain

4: x2 gain

5: x2.5 gain

6: x3 gain

7: x3.5 gain

ADC_gain

100[6:0]

Bit[6] = 1 (enable)

Bit[5:0] = ADC gain value (range 0 to 63)

The ADC value should be adjusted per clock speed to get the same response. The ADC unity gain value for 40MHz is

48, for 25MHz it is 54. Small differences between devices can occur, so ADC_gain matching can be needed to match

responses. In the plot below you can see the actual gain per ADC gain value.

In the plot below you can also see the relative gain versus the ADC_gain setting. It is recommended for the ADC_gain

value to stay within the limits of the plots or otherwise setting the ADC_gain too high or low will result in non-linear

behavior or image artifacts to occur.

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