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SLK2721IPZP bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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SLK2721IPZP bảng dữ liệu(HTML) 6 Page - Texas Instruments |
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6 / 21 page ![]() SLK2721 OC48+FEC/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER WITH ENHANCED JITTER TOLERANCE SLLS532 − JUNE 2002 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions(Continued) control/status pins (continued) TERMINAL TYPE DESCRIPTION NAME NO. TYPE DESCRIPTION SPILL 49 TTL output TX FIFO collision output TESTEN 43 TTL input (with pulldown) Production test mode enable. This pin must be left unconnected or tied low. voltage supply and reserved pins TERMINAL TYPE DESCRIPTION NAME NO. TYPE DESCRIPTION GND 1, 6, 19, 23, 26, 28, 30, 31, 33, 40 Ground Digital logic ground GNDA 10, 13 Ground Analog ground GNDLVDS 61, 69, 76, 77, 89, 93, 96, 100 Ground LVDS ground GNDPLL 12 Supply PLL ground RSVD 52 Reserved This pin needs to be tied to ground or left floating for normal operation. VDD 3, 22, 25, 29, 32, 35, 50 Supply Digital logic supply voltage (2.5 V) VDDA 7, 16 Supply Analog voltage supply (2.5 V) VDDLVDS 62, 72, 75, 78, 90, 91, 92, 97 Supply LVDS supply voltage (2.5 V) VDDPLL 11 Supply PLL voltage supply (2.5 V) |
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