MP2632 datasheet(35/37 Pages) MPS

35 / 37 page

MP2632

– ALL-IN-ONE, 3A SW CHARGER, 3A BOOST

MP2632 Rev.1.0

www.MonolithicPower.com

6/24/2016

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

In boost mode, CSYS is the output capacitor of the

boost converter. CSYS keeps the system voltage

ripple small and ensures feedback loop stability.

The system current ripple can be calculated with

Equation (18):

SYS _ MAX

RMS _ MAX

SYS _ MAX

V )





(18)

Since the input voltage is passed to the system

directly, VIN_MAX is equal to VSYS_MAX, and both

charge mode and boost mode have the same

system current ripple.

When ICC_MAX equals 2A, VTC equals 3V, VIN_MAX

equals 6V, and the maximum ripple current is 1A.

Select the system capacitors based on the ripple-

current temperature rise, not exceeding 10°C.

For best results, use low ESR ceramic capacitors

with X7R dielectrics and small temperature

coefficients. For most applications, use three

22µF capacitors.

Selecting the Battery Capacitor (CBATT)

CBATT is in parallel with the battery to absorb the

high-frequency switching ripple current. In charge

mode,

the

capacitor

(CBATT) is the output

capacitor of the buck converter. The output

voltage ripple is then calculated with Equation

(19):

BATT

SYS

BATT

1 V

/ V

8 C









(19)

In boost mode, CBATT is the input capacitor of the

boost converter. The input voltage ripple is the

same as the output voltage ripple from Equation

(19).

Both charge mode and boost mode have the

same battery voltage ripple. CBATT can be

calculated with Equation (20):

SYS _ MAX

BATT

BATT _ MAX

1 V

/ V





 



(20)

To guarantee ±0.5% BATT voltage accuracy, the

maximum BATT voltage ripple must not exceed

0.5% (e.g.: 0.1%). The worst case occurs at the

minimum battery voltage of the CC charge with

the

maximum

input

voltage.

For

example,

VSYS_MAX = 6V, VCC_MIN = VTC = 3V, L = 2.2µH, fS =

600kHz,

∆r

BATT_MAX = 0.1%, and CBATT is 22µF.

A 22µF ceramic capacitor with X7R dielectrics is

sufficient.

PCB Layout Guidelines

Efficient PCB layout is critical for meeting

specified

noise,

efficiency,

and

stability

requirements.

The

following

design

considerations can improve circuit performance:

1. Route the power stage adjacent to their

grounds.

2. Minimize the high-side switching node (SW,

inductor) trace lengths in the high-current

paths.

3. Keep the switching node short and away from

all

small

control

signals,

especially

the

feedback network.

4. Place the input capacitor as close to VIN and

PGND as possible.

5. Place

the

local

power

input

capacitors

connected from SYS to PGND as close to the

IC as possible.

6. Place the output inductor close to the IC.

7. Connect the output capacitor between the

inductor and PGND of the IC.

8. Connect the power pads for VIN, SYS, SW,

BATT, and PGND to as many coppers planes

on the board as possible for high-current

applications.

This

improves

thermal

performance

because the board conducts heat away

from the IC.

9. Connect a ground plane directly to the return

of all components through vias (e.g.: two vias

per capacitor for power-stage capacitors, and

one

via

per

capacitor

for

small-signal

components).

A star ground design approach is typically

used

keep

circuit

block

currents

isolated

(power-signal/control-signal),

which

reduces

noise-coupling

and

ground-bounce issues. A single ground

plane for this design provides good

results.

10. Place the ISET, OLIM, and ILIM resistors

very close to their respective IC pins.

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