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TLE7268LC bảng dữ liệu(PDF) 18 Page - Infineon Technologies AG

tên linh kiện TLE7268LC
Giải thích chi tiết về linh kiện  Dual LIN 2.2 / SAE J2602 Transceiver
PDF  34 Pages
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nhà sản xuất  INFINEON [Infineon Technologies AG]
Trang chủ  http://www.infineon.com
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TLE7268LC bảng dữ liệu(HTML) 18 Page - Infineon Technologies AG

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Data Sheet
18
Rev. 1.0
2017-09-14
TLE7268
Dual LIN 2.2 / SAE J2602 Transceiver
General product characteristics
6
General product characteristics
6.1
Absolute maximum ratings
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Table 3
Absolute maximum ratings 1)
All voltages with respect to ground; positive current flowing into pin; unless otherwise specified
1) Not subject to production test, specified by design
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Voltages
Battery supply voltage
VS
-0.3 –
40
V
ISO 17987 Param. 11
P_5.1.1
input voltage at BUS1, BUS2
VBUS
-27 –
40
V
–
P_5.1.2
DifferencevoltagebetweenBUS1
and BUS2
|VBUS1-BUS2|-
–
40
V
–
P_5.1.14
Logic voltage at EN1, EN2, TxD1,
TxD2, RxD1, RxD2
Vlogic
-0.3 –
6.0
V
–
P_5.1.3
INH voltage
VINH
-0.3 –
VS + 0.3 V
–
P_5.1.4
Currents
Output current at RxD1, RxD2
IRxD
0–
15
mA –
P_5.1.5
Output current at INH
IINH
-5
–
5
mA –
P_5.1.6
Temperatures
Junction temperature
Tj
-40 –
150
°C
–
P_5.1.7
Storage temperature
Ts
-55 –
150
°C
–
P_5.1.8
ESD Resistivity
Electrostaticdischarge voltage at
VS, BUS1, BUS2
VESD_HBM_BUS -8
–
8
kV
Human Body Model
(100pF via 1.5 kΩ)2)
2) ESD susceptibility HBM according to ANSI / ESDA / JEDEC JS-001
P_5.1.9
Electrostatic discharge voltage
all other pins
VESD_HBM_ALL -2
–
2
kV
Human Body Model
(100pF via 1.5 kΩ)2)
P_5.1.10
Electrostatic discharge voltage
corner pins
VESD_CDM_CP -750 –
750
V
Charged Device Model3)
3) ESD susceptibility, Charged Device Model “CDM” EIA / JESD 22-C101 or ESDA STM5.3.1
P_5.1.11
Electrostatic discharge voltage
all other pins
VESDCDM_OP -500 –
500
V
Charged Device Model3) P_5.1.12



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