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TLE8250 bảng dữ liệu(PDF) 7 Page - Infineon Technologies AG

tên linh kiện TLE8250
Giải thích chi tiết về linh kiện  High Speed CAN Transceiver
PDF  31 Pages
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nhà sản xuất  INFINEON [Infineon Technologies AG]
Trang chủ  http://www.infineon.com
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Data Sheet
7
Rev. 1.0
2016-07-15
TLE8250
High Speed CAN Transceiver
Functional Description
The is a High-Speed CAN transceiver, operating as an interface between the CAN controller and the physical
bus medium. A HS CAN network is a two wire, differential network which allows data transmission rates for
CAN FD frames up to 2 MBit/s. Characteristic for HS CAN networks are the two signal states on the HS CAN bus:
dominant and recessive (see Figure 3).
VCC and GND are the supply pins for the . The pins CANH and CANL are the interface to the HS CAN bus and
operate in both directions, as an input and as an output. RxD and TxD pins are the interface to the CAN
controller, the TxD pin is an input pin and the RxD pin is an output pin. The NEN and NRM pins are the input
pins for the mode selection (see Figure 4).
By setting the TxD input pin to logical “low” the transmitter of the drives a dominant signal to the CANH and
CANL pins. Setting TxD input to logical “high” turns off the transmitter and the output voltage on CANH and
CANL discharges towards the recessive level. The recessive output voltage is provided by the bus-biasing (see
Figure 1). The output of the transmitter is considered to be dominant, when the voltage difference between
CANH and CANL is at least higher than 1.5 V (VDiff = VCANH - VCANL).
Parallel to the transmitter the normal-mode receiver monitors the signal on the CANH and CANL pins and
indicates it on the RxD output pin. A dominant signal on the CANH and CANL pins sets the RxD output pin to
logical “low”, vice versa a recessive signal sets the RxD output to logical “high”. The normal-mode receiver
considers a voltage difference (VDiff) between CANH and CANL above 0.9 V as dominant and below 0.5 V as
recessive.
To be conform with HS CAN features, like the bit to bit arbitration, the signal on the RxD output has to follow
the signal on the TxD input within a defined loop delay tLoop ≤ 255 ns.



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