ICS840001 datasheet(7/12 Pages) ICST

7 / 12 page

840001BG

www.icst.com/products/hiperclocks.html

REV. A MAY 10, 2004

Integrated

Circuit

Systems, Inc.

ICS840001

FEMTOCLOCKS™CRYSTAL-TO-

LVCMOS/LVTTL CLOCK GENERATOR

APPLICATION INFORMATION

Figure 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS840001 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2 below were determined using a 26.5625MHz, 18pF par-

allel resonant crystal and were chosen to minimize the ppm er-

ror. The optimum C1 and C2 values can be slightly adjusted for

different board layouts.

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. The ICS840001 provides separate

power supplies to isolate any high switching noise from the out-

puts to the internal PLL.V

DD, and VDDA should be individually con-

nected to the power supply plane through vias, and bypass ca-

pacitors should be used for each pin. To achieve optimum

jitter performance, power supply isolation is required.

Figure 1

illustrates how a 10

Ω resistor along with a 10µF and a .01µF

bypass capacitor should be connected to each V

DDA pin.

POWER SUPPLY FILTERING TECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

Ω

DDA

µF

.01

µF

3.3V

.01

µF

33p

18pF Parallel Crystal

27p

XTAL_OUT

XTAL_IN

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