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ISL6410AIU bảng dữ liệu(PDF) 21 Page - Renesas Technology Corp

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Giải thích chi tiết về linh kiện  Single Synchronous Buck Regulators with Integrated FET
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ISL6410, ISL6410A
FN9149 Rev 3.00
Page 8 of 13
September 17, 2004
Power Good
This output is asserted high when the PWM is enabled, and
Vout is within 8.0% typical of its final value, and is active low
outside this range. When disabled, the output turns active low.
It is recommended to leave the PG pin unconnected when not
used.
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM
cycle, exceeding the overcurrent limit, causes a 4 bit up/down
counter to increment by one LSB. A normal current state
causes the counter to decrement by one LSB (the counter will
not however “rollover” or count below 0000). When the PWM
goes into overcurrent, the counter rapidly reaches count 1111
and the PWM output is shut down and the soft-start counter is
reset. After 16 clocks the PWM output is enabled and the soft-
start cycle is started.
If Vout exceeds the overvoltage limit for 32 consecutive clock
cycles the PWM output is shut off and the soft-start cycle is
initiated.
No Load Operation
If there is no load connected to the output, the converter will
regulate the output voltage by allowing the inductor current to
reverse for a short period of time.
Output Capacitor Selection
For best performance, a low ESR output capacitor is needed.
Output voltages below 1.8V require a larger output capacitor
and ESR value to improve the performance and stability of the
converter. For 1.8V output applications, a ceramic capacitor of
10µF or higher value with ESR
50m is recommended.
The RMS ripple current is calculated as:
L = the inductor value
f = the switching frequency
The overall output ripple voltage is the sum of the voltage spike
caused by the output capacitor ESR and the voltage ripple
caused by charge and discharge of the output capacitor:
Where the highest output voltage ripple occurs at the highest
input voltage VIN.
Input Capacitor Selection
The input current to the buck converter is pulsed, and therefore
a low ESR input capacitor is required. This results in good
input voltage filtering and minimizes the interference it causes
to other circuits. The input capacitor should have a minimum
value of 10
F and a higher value can be selected for improving
input voltage filtering. The input capacitor should be rated for
the maximum input ripple current calculated as:
The worst case RMS ripple current occurs at D = 0.5 and is
calculated as: Irms = Io/2.
D = Duty Cycle
Ceramic capacitors are preferred because of their low ESR
value. They are also less sensitive to voltage transients when
compared to tantalum capacitors. It is good practice to place
the input capacitor as close as possible to the input pin of the
IC for optimum performance.
Inductor Selection
The ISL6410 is an internally compensated device and hence a
minimum of 8.2
H must be used for the ISL6410 and a
minimum of 12
H for the ISL6410A. The selected inductor
must have a low DC resistance and a saturation current
greater than the maximum inductor current value can be
calculated from the equations below
where
dIL = the peak to peak inductor current
L = the inductor value
f = the switching frequency
ILmax = the max inductor current
TABLE 2. RECOMMENDED OUTPUT CAPACITORS
CAPACITOR
VALUE
ESR
(m

COMPONENT
SUPPLIER
COMMENTS
10
F
<50 AVX 08056D106KAT2A
Ceramic
IRMS Co

Vo
1
Vo
Vin
---------
–
Lf
-------------------
1
23
-----------------
=
Vo
Vo
1
Vo
Vin
---------
–
Lf
-------------------
1
8Cof
------------------------- ESR
+


=
TABLE 3. RECOMMENDED INDUCTORS
INDUCTOR VALUE
DCR (m

COMPONENT
SUPPLIER
8.2
H75
Coilcraft
MSS6122-822MX
12
H
100
Coilcraft
MSS6122-123MX
IRMS
Io max

Vo
Vin
---------
1
Vo
Vin
---------
–


=
dIL
Vo
1
Vo
Vin
---------
–
Lf
-------------------
=
IL max
Io max
dIL
2
---------
+
=



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