HSP50214BVCZ datasheet(49/62 Pages) RENESAS

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HSP50214B

FN4450 Rev 4.00

Page 49 of 62

May 1, 2007

CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

31-22

Reserved

Reserved.

Enable External



Filter Sync

0- The SYNCIN2 pin has no effect on the halfband and FIR filters.

1- When the SYNCIN2 pin is asserted, the filter control circuitry in the halfband filters, the FIR, the

resampler, and the discriminator are reset. SYNCIN2 can be used to synchronize the computations of

the filters in multiple parts for the alignment (see Synchronization Section).

Halfband (HB)



Bypass

1- Bypass Halfband Filters.

0- Enable HB Filters (at least one HB must be enabled).

HB5 Enable

0- Disables HB number 5 (the last in the cascade).

1- Enables HB filter number 5.

HB4 Enable

Setting this bit enables HB filter number 4.

HB3 Enable

Setting this bit enables HB filter number 3.

HB2 Enable

Setting this bit enables HB filter number 2.

HB1 Enable

Setting this bit enables HB filter number 1.

14-11

FIR Decimation

Load decimation from 1-16, where 0000 = 16. Bit 14 is the MSB.

0001 - 1

1001 - 9

0010 - 2

1010 - 10

0011 - 3

1011 - 11

0100 - 4

1100 - 12

0101 - 5

1101 - 13

0110 - 6

1110 - 14

0111 - 7

1111 - 15

1000 - 8

0000 - 16

FIR Real/Complex

0- Complex Filter.

1- Dual Real Filters.

FIR Sym Type

0- Odd Symmetry.

1- Even Symmetry.

FIR Symmetry

0- Symmetric Filters.

1- Asymmetric Filters.

7-0

FIR Taps

Number of taps in the FIR filter. Range is 1 to 255, where 0000000 is invalid.

CONTROL WORD 8: AGC CONFIGURATION 1 (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

31-30

Reserved

Reserved.

Sync AGC Updates to

SYNCIN2

When this bit is 1, the SYNCIN2 pin loads the contents of the master registers into the AGC accumulator.

28-16

Threshold

The magnitude measurement out of the cartesian to polar converter is subtracted from this value to get

the gain error. A gain of 1.647 in the cartesian to polar conversion that must be taken into account when

computing this threshold. These bits are weighted -22 down to 2-10. Bit 28 is the MSB.

15-12

Loop Gain 1



Mantissa

Selected when AGCGNSEL = 1. These bits, MMMM, together with the exponent bits, EEEE (11-8), set

the loop gain for the AGC loop. The gain adjustment per output sample is:

1.5dB (Threshold -[Magnitude * 1.6]) 0.MMMM * 2-(15 - EEEE) where magnitude ranges from 0 to 1.414

and the threshold is programmed in bits 28-16. The decimal value for the mantissa is calculated as

DEC(MMMM)/16. Bit 15 is the MSB.

11-8

Loop Gain 1



Exponent

Selected when AGCGNSEL = 1. These bits are EEEE. See description of bits 15-12. Bit 11 is the MSB.

7-4

Loop Gain 0 Mantissa

Selected when AGCGNSEL = 0. These bits are MMMM. See description for bits 15-12. Same equations

are used for Loop 0. Bit 7 is the MSB.

3-0

Loop Gain 0



Exponent

Selected when AGCGNSEL = 0. These bits are EEEE. See description for bits 15-12. Same equations

are used for Loop 0. Bit 3 is the MSB.

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