LTC2636 datasheet(22/28 Pages) LINER

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LTC2668

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operation

A, while channels whose toggle select bits are 1 update

from input register B (see Figure 8). By alternating toggle-

select and update operations, up to 16 channels can be

simultaneously switched to A or B as needed.

Daisy-Chain Operation

The serial output of the shift register appears at the SDO

pin. Data transferred to the device from the SDI input is

delayed 32 SCK rising edges before being output at the

next SCK falling edge, suitable for clocking into the mi-

croprocessor on the next 32 SCK rising edges.

The SDO output can be used to facilitate control of multiple

serial devices from a single 3-wire serial port (i.e., SCK,

SDI and CS/LD). Such a daisy-chain series is configured

by connecting the SDO of each upstream device to the SDI

of the next device in the chain. The shift registers of the

devices are thus connected in series, effectively forming a

single input shift register which extends through the entire

chain. Because of this, the devices can be addressed and

controlled individually by simply concatenating their input

words; the first instruction addresses the last device in

the chain and so forth. The SCK and CS/LD signals are

common to all devices in the series.

In use, CS/LD is first taken low. Then, the concatenated

input data is transferred to the chain, using the SDI of the

first device as the data input. When the data transfer is

complete, CS/LD is taken high, completing the instruction

sequence for all devices simultaneously. A single device

can be controlled by using the No-Operation command

(1111) for all other devices in the chain.

When CS/LD is taken high, the SDO pin presents a high

impedance output, so a pull-up resistor is required at

the SDO of each device (except the last) for daisy-chain

operation.

Echo Readback

The SDO pin can be used to verify data transfer to the

device. During each 32-bit instruction cycle, SDO outputs

the previous 32-bit instruction for verification.

When CS/LD is high, SDO presents a high impedance

output, releasing the bus for use by other SPI devices.

Power-Down Mode

Forpower-constrainedapplications,power-downmodecan

be used to reduce the supply current whenever less than

sixteen DAC outputs are needed. When in power-down,

the output amplifiers and reference buffers are disabled.

The DAC outputs are put into a high impedance state, and

the output pins are passively pulled to ground through

individual 42k (minimum) resistors. Register contents

are not disturbed during power-down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in combina-

tion with the appropriate DAC address. In addition, all the

DACchannelsandtheintegratedreferencetogethercanbe

put into power-down mode using the

Power-Down Chip

command, 0101b. The 16-bit data word is ignored for all

power-down commands.

Normal operation resumes by executing any command

which includes a DAC update—either in software, as

shown in Table 1, by taking the asynchronous LDAC pin

low, or by toggling (see the Types of Toggle Operations

section). The selected DAC is powered up as its voltage

output is updated. When updating a powered-down DAC,

add wait time to accommodate the extra power-up delay. If

the channels have been powered down (command 0100b)

prior to the update command, the power-up delay time is

30μs. If, on the other hand, the chip has been powered

down(command0101b),thepower-updelaytimeis35μs.

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 1, the

asynchronous, active-low LDAC pin updates all 16 DAC

registers with the contents of the input registers.

If CS/LD is high, a low on the LDAC pin causes all DAC

registers to be updated with the contents of the input

registers.

If CS/LD is low, a low-going pulse on the LDAC pin be-

fore the rising edge of CS/LD powers up all DAC outputs,

but does not cause the outputs to be updated. If LDAC

remains low after the rising edge of CS/LD, then LDAC is

recognized, the command specified in the 24-bit word is

executed and the DAC outputs are updated.

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