LTM2893 datasheet(21/32 Pages) LINER

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LTM2893/LTM2893-1

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TIMING DIAGRAMS

SAMPLING RATE

Achieving a specified sampling rate is the typical goal for

systems integrating ADCs. The LTM2893 adds a small

amount of overhead to the sampling rate or ADC CYCLE

TIME. The selection of the SCK2 frequency and the master

SCK frequency will impact the overall time in-between

CNVs. The following is a description of each timing

characteristic to be calculated to achieve a sampling rate.

1. tDCNV: the delay from CNV to CNV2, maximum of 28ns,

is the delay before the ADC receives a conversion start

signal.

2. tCNV2toADCstart: the ADC aperture delay or the CNV to

BUSY delay of the ADC.

3. tCNVADC: the conversion time of the ADC, duration of

the ADC's BUSY signal.

4. tBUSY2FBUSYF: LTM2893 delay in buffering the first

2 bits from the ADC. tBUSY2FBUSYF = tBUSY2FSS2F +

tSS2FSCK2 + 1 • tSCK2. tSS2FSCK2 is 3 • tSCK2 when SCK2

frequency = 100MHz or 66MHz, 2 • tSCK2 when SCK2

frequency = 50MHz to 25MHz, or 1 • tSCK2 when SCK2

frequency is 12.5MHz or 6.25MHz.

5. tBUSYFSCKR:timebetweenthemasterresponsetoBUSY

falling and the first SCK rising edge. If SS is always low

reference Table 2. If SS is used, reference the timing

in Table 2 for BUSY falling to the SCK rising edge with

the additional requirement that a minimum time from

SS falling to SCK rising, tSSFSCK, is maintained.

6. tDATAREAD: ((WORD COUNT • WORDLENGTH)-1)/(SCK

frequency) is the time for the master to read the data

from the SPI port.

7. tSCKSSDIS:delayfromlastSCKrisingedgetotherelease

of SS, minimum of 20ns.

8. tCRC: 0ns if CRCENA = 0, 225ns if CRCENA=1.

9. tQUIET: space between the SS rising edge and the next

CNV rising edge, minimum of 20ns.

The minimum sampling time is the sum of these timing

characteristicsforaselectedSCK2frequencyandamaster

SCK frequency. The following equation defines this mini-

mum sample time (2893ADC CYCLE TIMEMIN), assuming

SCK frequency ≤ SCK2 frequency. Figure 9 shows the

relationship of these parameters to a conversion cycle.

2893ADC CYCLE TIMEMIN = tDCNV + tCNV2toADCstart + tC-

NVADC + tBUSY2FBUSYF + tBUSYFSCKR + tDATAREAD + tSCKSSDIS

+ tCRC + tQUIET

LOGIC INTERFACE

The LTM2893 logic side interface is similar to an ADC that

has a conversion start and busy control signals. Figure 9

showstheinteractionofcontrolsignalsCNV,BUSY,andthe

SPI serial interface. The CNV transition starts the process

and BUSY responds to indicate the ADC is converting a

result and masking the propagation delay of signals pro-

cessed through the isolation barrier. The BUSY signal is up

to 95ns longer than the ADC’s BUSY signal (when SCK2

Figure 8. Writing Configuration Registers Timing Diagram

CONFIGURING THE LTM2893 WITH CSC CHIP SELECT LOGIC SIDE INTERFACE

CSC

SCK

MOSI

AD7

tSCK

tSCKH tSCKL

tCSCFSCK

AD7

CNV = 0, SS = VL

SA, SB, SC STATIC

2893 F08

tSCKCSCDIS

tCSCSPACE

tDIS

tHDMOSI

tSUMOSI

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