COP682C datasheet(17/30 Pages) NSC

17 / 30 page

Control Registers

CNTRL REGISTER (ADDRESS X’00EE)

The Timer and MICROWIREPLUS control register contains

the following bits

SL1

SL0 Select the MICROWIREPLUS clock divide-by

IEDG

External interrupt edge polarity select

(0 e rising edge 1 e falling edge)

MSEL

Enable MICROWIREPLUS functions SO and

TRUN

StartStop the TimerCounter (1 e run 0 e

stop)

TC3

Timer input edge polarity select (0 e rising

edge 1 e falling edge)

TC2

Selects the capture mode

TC1

Selects the timer mode

TC1

TC2

TC3

TRUN

MSEL

IEDG

SL1

SL0

BIT 7

BIT 0

PSW REGISTER (ADDRESS X’00EF)

The PSW register contains the following select bits

GIE

Global interrupt enable

ENI

External interrupt enable

BUSY MICROWIREPLUS busy shifting

IPND

External interrupt pending

ENTI

Timer interrupt enable

TPND Timer interrupt pending

Carry Flag

Half carry Flag

TPND

ENTI

IPND

BUSY

ENI

GIE

Bit 7

Bit 0

Addressing Modes

This is the ‘‘normal’’ mode of addressing The operand is

the memory addressed by the B register or X register

DIRECT

The instruction contains an 8-bit address field that directly

points to the data memory for the operand

IMMEDIATE

The instruction contains an 8-bit immediate field as the op-

erand

(AUTO INCREMENT AND DECREMENT)

This is a register indirect mode that automatically incre-

ments or decrements the B or X register after executing the

instruction

RELATIVE

This mode is used for the JP instruction the instruction field

is added to the program counter to get the new program

location JP has a range of from b31 to a32 to allow a one

byte relative jump (JP a 1 is implemented by a NOP instruc-

tion) There are no ‘pages’ when using JP all 15 bits of PC

are used

Memory Map

All RAM ports and registers (except A and PC) are mapped

into data memory address space

Address

Contents

00 to 6F On Chip RAM Bytes

70 to 7F Unused RAM Address Space (Reads as all Ones)

80 to BF Expansion Space for future use

C0 to CF Expansion Space for IO and Registers

D0 to DF On Chip IO and Registers

Port L Data Register

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

Port G Data Register

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

Port C Data Register

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved for Port C

Port D Data Register

DD – DF Reserved for Port D

E0 to EF On Chip Functions and Registers

E0 – E7 Reserved for Future Parts

Reserved

MICROWIREPLUS Shift Register

Timer Lower Byte

Timer Upper Byte

Timer Autoload Register Lower Byte

Timer Autoload Register Upper Byte

CNTRL Control Register

PSW Register

F0 to FF On Chip RAM Mapped as Registers

X Register

SP Register

B Register

Reading unused memory locations below 7FH will return all

ones Reading other unused memory locations will return

undefined data

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