STK14D88

April 2005

Document Control #ML0033 rev 1.2

7

MODE SELECTION

E

W

G

MODE

I/O

POWER

NOTES

H

X

X

X

Not Selected

Output High Z

Standby

L

H

L

X

Read SRAM

Output Data

Active

L

L

X

X

Write SRAM

Input Data

Active

L

H

L

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x03F8

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Autostore Disable

Output Data

Output Data

Output Data

Output Data

Output Data

Output Data

Active

i

, j, k

L

H

L

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x07F0

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Autostore Enable

Output Data

Output Data

Output Data

Output Data

Output Data

Output Data

Active

i

, j, k

L

H

L

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0FC0

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile Store

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

ICC2

i

, j, k

L

H

L

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0C63

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile Recall

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

i

, j, k

Notes

i: The six consecutive addresses must be in the order listed. W

must be high during all six consecutive cycles to enable a nonvolatile cycle.

j: While there are 15 addresses on the STK14D88, only the lower 14 are used to control software modes

k: I/O state depends on the state of G . The I/O table shown assumes G

low.