EM78P257 datasheet(13/91 Pages) EMC

13 / 91 page

EM78P257

OTP ROM

This specification is subject to change without prior notice.

07.27.2004 (V1.4)

Address

R PAGE registers

IOCX0 PAGE registers

(Indirect Addressing Register)

Reserve

(Time Clock Counter)

CONT (Control Register)

(Program Counter)

Reserve

(Status Register)

Reserve

(RAM Select Register)

Reserve

(Port5)

IOC50 (I/O Port Control Register)

(Port6)

IOC60 (I/O Port Control Register)

(Port7)

IOC70 (I/O Port Control Register)

Reserve

IOCB0

(Pull-down Control

IOCF0 (Interrupt Mask Register)

︰

General Registers

：

Bank0

Bank1

IOCX1 PAGE registers

IOC80

(TCC Control Register)

IOC90

(CMP Control Register)

IOCA0

(CO-Input Combine

sequence)

IOCC0

(Open-drain Control

IOCD0 (Pull-high Control Register)

IOCE0 (WDT Control Register)

IOC51

(TCCA Counter)

IOC61

(TCCBL Counter)

IOC71

(TCCBH Counter)

IOC81

(TCCC Counter)

IOC91

(Low-time Register)

IOCA1

(High-time Register)

IOCB1

(Pulse time Register)

Reserve

(CMPOUT Status Register

& TCC Status Register)

(TCC Control Register(1))

(TCC Control Register(2))

(TCC Prescaler Register)

(IR Control Register)

(Mouse Control Register)

(Interrupt Status Register)

Fig. 5 Data memory configuration

4. R3 (Status Register)

RST

IOCS

PS0

• Bit 7 (RST) Bit for reset type.

Set to 1 if wake-up from sleep on pin change or comparator status change.

Set to 0 if wake-up from other reset types

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