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MP8763DGL bảng dữ liệu(PDF) 15 Page - Monolithic Power Systems |
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MP8763DGL bảng dữ liệu(HTML) 15 Page - Monolithic Power Systems |
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15 / 25 page ![]() MP8763D ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER MP8763D Rev. 1.1 www.MonolithicPower.com 15 1/15/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. R1 R2 ESR POSCAP SW VOUT L FB Figure 6—Simplified Circuit in PWM Mode without External Ramp Compensation To realize the stability without an external ramp, usually select the ESR value as follows: OUT ON SW ESR C 2 T 7 . 0 T R + π × ≥ (4) Where TSW is the switching period. Ramp with a Small ESR Capacitor Use an external ramp when using ceramic output capacitors, because the ESR ripple is not high enough to stabilize the system. R1 R2 Ceramic SW FB VOUT L R4 C4 IR4 IC4 IFB R9 Figure 7—Simplified Circuit in PWM Mode with External Ramp Compensation Figure 7 shows the simplified circuit in PWM mode with the HS-FET OFF and an external ramp compensation circuit (R4, C4). Design the external ramp based on the inductor ripple current. Select C4, R9, R1 and R2 to meet the following condition: ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + + × × < × × π 9 R 2 R 1 R 2 R 1 R 5 1 4 C F 2 1 SW (5) Where: 4 C FB 4 C 4 R I I I I ≈ + = (6) Then estimate the ramp on VFB as: ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + × × × − = 9 R 2 R // 1 R 2 R // 1 R T 4 C 4 R V V V ON OUT IN RAMP (7) The VFB ripple’s descending slope then follows: 4 C 4 R V T V V OUT OFF RAMP 1 SLOPE × − = = (8) Equation 8 shows that if there is instability in PWM mode, reduce either R4 or C4. If C4 is irreducible due to equation 5 limitations, then reduce R4. For a stable PWM operation, design Vslope1 based on equation 9. SW ON 3 ESR OUT OUT SLOPE1 OUT OUT SW ON TT RC I10 0.7 2 VV 2L C T T − +− × × ×π −≥ × + ×× − (9) Where IOUT is the load current. In skip mode, The VFB ripple’s descending slope is almost same whether the external ramp is used or not. Figure 8 shows the simplified circuit in skip mode when both the HS-FET and LS-FET are off. R1 R2 COUT FB VOUT ROUT Figure 8—Simplified Circuit in skip Mode Determine the VFB ripple’s descending slope in skip mode as follows: OUT OUT REF 2 SLOPE C ] R // ) 2 R 1 R [( V V × + − = (10) Where ROUT is the equivalent load resistor. Figure 5 shows that VSLOPE2 in skip mode is lower than that is in PWM mode, so it is |
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