MP8126 – LNB POWER SUPPLY AND CONTROL VOLTAGE REGULATOR

MP8126 Rev. 1.03

www.MonolithicPower.com

10

5/27/2013

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© 2013 MPS. All Rights Reserved.

APPLICATION INFORMATION

COMPONENT SELECTION

Selecting the Input Capacitor

The input capacitor (C1) is required to maintain

the DC input voltage. For best results, use

ceramic capacitors with low ESR/ESL. Estimate

the input voltage ripple using the formula below:

IN

IN

IN

2

sOUT

VV

V1

8f L C1

V

⎛⎞

Δ=

⋅ −

⎜⎟

⋅⋅

⎝⎠

A 10μF X7R ceramic capacitor is recommended

for most application.

Setting the Output Boost Converter Capacitor

The output current of the step-up converter is

discontinuous, and therefore requires a capacitor

to supply the AC current to the load. Use low-

ESR capacitors for the best performance. The

output voltage ripple can be estimated by the

below formula.

OUT

IN

OUT

sL

OUT

V

V

V1

fR C2

V

⎛⎞

Δ=

⋅ −

⎜⎟

⋅⋅

⎝⎠

Ceramic capacitors with X7R dielectrics are

highly recommended because of their low ESR

and small temperature coefficient. Typically, a

22μF X7R ceramic capacitor is recommended.

Select an inductor with a DC current rating that is

at least 25% higher than the maximum load

current. For most designs, derive the inductance

value from the following equation.

IN

OUT

IN

sOUT

L

V(V

V )

L

fV

I

−

=

⋅⋅ Δ

the inductor ripple current to be approximately

30% of the maximum load current.

Selecting the Boost Converter Rectifier Diode

The high switching frequency requires high-

speed rectifiers, such as Schottky diodes for their

fast recovery times and low forward voltage. For

most applications, use a 2A Schottky diode.

DESIGN EXAMPLE

Below is a design example that follows the

application

guidelines

for

the

following

specifications:

12V

19V

Figure

4

shows

the

detailed

application

schematic. The typical performance and circuit

waveforms have been shown in the Typical

Performance Characteristics section. For more

applications, please refer to the Evaluation Board

Data Sheet.

LAYOUT RECOMMENDATION

Layout is important, poor layout results in

reduced performance, EMI problems, resistive

loss, and even system instability. Following the

below rules and figure 3 for the layout design:

1. Place high current path(SW, D1, C2 and IC-

PGND) very close to the device with short,

direct and wide traces.

2. Place the decoupling capacitor C3 across

VDD and SGND as close as possible.

3. Place the decoupling capacitor C4 across

BYPASS and SGND as close as possible.

4. Place the LDO input/output capacitor C11/C8

across VBOOST/VOUT and PGND as close

as possible.

5. Place capacitor C7 across TCAP and SGND

pins as close as possible.

6. Keep the switching node (SW) plane as small

as possible and far away from the TCAP and

ILIMT trace.

7. Add copper and vias on GND net around the

device to help dissipate heat. The PGND and

SGND should be connected through a star

ground.