The Smart Timing Choice



The Smart Timing Choice



SiT2018B

High Temp, Single-Chip, One-Output Clock Generator

Rev. 1.0

Page 7 of 12

www.sitime.com

Programmable Drive Strength

The SiT2018 includes a programmable drive strength feature

to provide a simple, flexible tool to optimize the clock rise/fall

time for specific applications. Benefits from the programmable

drive strength feature are:

• Improves system radiated electromagnetic interference

(EMI) by slowing down the clock rise/fall time

• Improves the downstream clock receiver’s (RX) jitter by de-

creasing (speeding up) the clock rise/fall time.

• Ability to drive large capacitive loads while maintaining full

swing with sharp edge rates.

For more detailed information about rise/fall time control and

drive strength selection, see the SiTime Application Notes

EMI Reduction by Slowing Rise/Fall Time

Figure 16 shows the harmonic power reduction as the rise/fall

times are increased (slowed down). The rise/fall times are

expressed as a ratio of the clock period. For the ratio of 0.05,

the signal is very close to a square wave. For the ratio of 0.45,

the rise/fall times are very close to near-triangular waveform.

These results, for example, show that the 11th clock harmonic

can be reduced by 35 dB if the rise/fall edge is increased from

5% of the period to 45% of the period.

Figure 16. Harmonic EMI reduction as a Function of

Slower Rise/Fall Time

Jitter Reduction with Faster Rise/Fall Time

Power supply noise can be a source of jitter for the

downstream chipset. One way to reduce this jitter is to speed

up the rise/fall time of the input clock. Some chipsets may also

require faster rise/fall time in order to reduce their sensitivity to

this type of jitter. Refer to the Rise/Fall Time Tables (Table 7 to

Table 11) to determine the proper drive strength.

High Output Load Capability

The rise/fall time of the input clock varies as a function of the

actual capacitive load the clock drives. At any given drive

strength, the rise/fall time becomes slower as the output load

increases. As an example, for a 3.3V SiT2018 device with

default drive strength setting, the typical rise/fall time is 1ns for

15 pF output load. The typical rise/fall time slows down to

2.6 ns when the output load increases to 45 pF. One can

choose to speed up the rise/fall time to 1.83 ns by then

increasing the drive strength setting on the SiT2018.

The SiT2018 can support up to 60 pF in maximum capacitive

loads with drive strength settings. Refer to the Rise/Tall Time

Tables (Table 7 to 11) to determine the proper drive strength

for the desired combination of output load vs. rise/fall time

SiT2018 Drive Strength Selection

Tables 7 through 11 define the rise/fall time for a given capac-

itive load and supply voltage.

1. Select the table that matches the SiT2018 nominal supply

voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V).

2. Select the capacitive load column that matches the appli-

cation requirement (5 pF to 60 pF)

3. Under the capacitive load column, select the desired

rise/fall times.

4. The left-most column represents the part number code for

the corresponding drive strength.

5. Add the drive strength code to the part number for ordering

purposes.

Calculating Maximum Frequency

Based on the rise and fall time data given in Tables 7 through

11, the maximum frequency the oscillator can operate with

guaranteed full swing of the output voltage over temperature

can be calculated as the following:

where Trf_20/80 is the typical value for 20%-80% rise/fall

time.

Example 1

• Vdd = 1.8V (Table 7)

• Capacitive Load: 30 pF

• Desired Tr/f time = 3 ns (rise/fall time part number code = E)

Part number for the above example:

SiT2018BIES2-18E-66.666660

Drive strength code is inserted here. Default setting is “-”

 

1

3579

11

-80

-70

-60

-50

-40

-30

-20

-10

0

10

Harm onic number

trise=0.05

trise=0.1

trise=0.15

trise=0.2

trise=0.25

trise=0.3

trise=0.35

trise=0.4

trise=0.45

=

1

5 x T rf_ 2 0 /8 0

M a x F re que ncy