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MP8847GD bảng dữ liệu(PDF) 6 Page - Monolithic Power Systems |
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MP8847GD bảng dữ liệu(HTML) 6 Page - Monolithic Power Systems |
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6 / 22 page ![]() MP8847 – 6A, 2.7V-6V, HIGH-EFFICIENCY, SYNCHRONOUS STEP-DOWN SWITCHER WITH I 2C INTERFACE IN 2X3MM QFN MP8847 Rev. 1.02 www.MonolithicPower.com 6 12/28/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. I/O LEVEL CHARACTERISTICS Parameter Symbol Condition HS-Mode LS-Mode Units Min Max Min Max Low-level input voltage VIL -0.5 0.3VCC -0.5 0.3Vcc V High-level input voltage VIH 0.7VCC VCC+0.5 0.7VCC VCC+0.5 V Hysteresis of Schmitt trigger inputs VHYS VCC>2V 0.05VCC - 0.05VCC - V VCC<2V 0.1VCC - 0.1VCC - Low-level output voltage(open drain) at 3mA sink current VOL VCC>2V 0 0.4 0 0.4 V VCC<2V 0 0.2VCC 0 0.2Vcc Low-level output current IOL - 3 - 3 mA Transfer gate on resistance for currents between SDA and SCAH, or SCL and SCLH RonL VOL level, IOL=3mA - 50 - 50 Ω Transfer gate on resistance between SDA and SCAH, or SCL and SCLH RonH Both signals (SDA and SDAH, or SCL and SCLH) at VCC level 50 - 50 - kΩ Pull-up current of the SCLH current source Ics SCLH output levels between 0.3VCC and 0.7VCC 2 6 2 6 mA Rise time of the SCLH or SCL signal trCL Output rise time (current source enabled) with an external pull-up current source of 3mA Capacitive load from 10pF to 100pF 10 40 ns Capacitive load of 400pF 20 80 ns Fall time of the SCLH or SCL signal tfCL Output fall time (current source enabled) with an external pull-up current source of 3mA Capacitive load from 10pF to 100pF 10 40 ns Capacitive load of 400pF 20 80 20 250 ns Rise time of SDAH signal trDA Capacitive load from 10pF to 100pF 10 80 - - ns Capacitive load of 400pF 20 160 20 250 ns Fall time of SDAH signal tfDA Capacitive load from 10pF to 100pF 10 80 - - ns Capacitive load of 400pF 20 160 20 250 ns |
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