MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER

MP2269 Rev. 1.0

www.MonolithicPower.com

15

10/11/2016

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The

input

voltage

ripple

caused

by

the

capacitance can be estimated with Equation (8):

LOAD

OUT

OUT

IN

IN

S

IN

I

V

V

V1

f

C1

V

V









 







(8)

Selecting the Output Capacitor

The output capacitor (C2) maintains the DC

output voltage. Use ceramic, tantalum, or low

ESR electrolytic capacitors. For best results,

use low ESR capacitors to keep the output

voltage ripple low. The output voltage ripple can

be estimated with Equation (9):

OUT

OUT

OUT

ESR

S

1

IN

S

VV

1

V

1

R

f

L

V

8 f

C2









 











 

 

(9)

equivalent series resistance (ESR) value of the

output capacitor.

For

ceramic

capacitors,

the

capacitance

dominates the impedance at the switching

frequency, and the capacitance causes the

majority of the output voltage ripple. For

simplification, the output voltage ripple can be

estimated with Equation (10):

OUT

OUT

OUT

2

IN

S1

VV

ΔV

1

V

8 f

L

C2





 





 



(10)

For tantalum or electrolytic capacitors, the ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be approximated with Equation (11):

OUT

OUT

OUT

ESR

IN

S1

VV

ΔV

1

R

f

L

V





 









(11)

The characteristics of the output capacitor

affect the stability of the regulation system. The

MP2269 can be optimized for a wide range of

capacitance and ESR values.

Efficient

PCB

layout

is

critical for

stable

operation. For best results, refer to Figure 6 and

follow the guidelines below.

1. Keep the connection of the input ground

and GND as short and wide as possible.

2. Keep the connection of the input capacitor

and VIN as short and wide as possible.

3. Ensure all feedback connections are short

and direct.

4. Place

the

feedback

resistors

and

compensation components as close to the

chip as possible.

5. Route SW away from sensitive analog

areas such as FB.

NOTES:

8) The recommended layout is based on the Typical Application

circuit on page 17 and page 18.

GND

GND

VOUT

VIN

Top Layer

GND

Bottom Layer

Figure 6: Sample PCB Layout