PCI9080 datasheet(36/133 Pages) ETC

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SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 28

Version 0.93

3.10 INTERRUPTS

LINTo#

DMA Ch 0 Done

DMA Ch 1 Done

Doorbells

Mailboxes

BIST

Messaging Queue

[17]

[7]

[23]

DMA Ch 1

Terminal Count

LSERR#

Master Abort

256 Retrys

Target Abort

Parity Error

Messaging Queue

Doorbells

Master Abort

256 Retrys

Target Abort

LINTi#

Messaging Queue

[1]

[0]

[12]

[9]

[10]

[11]

[12]

INTA#

DMA Ch 0 Done

DMA Ch 0

Terminal Count

DMA Ch 1 Done

DMA Ch 1

Terminal Count

DMA Ch 0

Terminal Count

[8]

[16]

The # represent the bit # of register (LOC [E8h])

X1 = Bit [7:6] of register (LOC [168h])

X2 = Bit [10] of register (LOC [100h])

X3 = Bit [2] of register (LOC [E110h])

X4 = Bit [18] of register (LOC [E8h]) & Bit [17] of register (LOC [100h])

X5 = Bit [5:4] of register (LOC [168h])

X7 = Bit [2] of register (LOC [124h])

X6 = Bit [10] of register (LOC [114h])

X8 = Bit [19] of register (LOC [E8h]) & Bit [17] of register (LOC [114h])

X9 = Bit [3] of register (LOC [B0h]) & Bit [3] of register (LOC [B4h])

For X4 & X8, if the bit [17]='0' then LINTo# is generated and

if the bit [17]='1' then INTA# is generated.

Figure 3-11. Interrupt and Error Sources

3.10.1 PCI Interrupts (INTA#)

A PCI 9080 PCI Interrupt (INTA#) can be generated by

one of the following:

•

Local to PCI doorbell register

•

Local interrupt input

•

Master/target abort status condition

•

DMA Ch 0/Ch 1 Done

•

DMA Ch 0/Ch 1 Terminal Count reached

•

Messaging Outbound Post Queue Not Empty

INTA#, or individual sources of an interrupt, can be

enabled or disabled with the PCI 9080 Interrupt

Control/Status Register. The Interrupt Control/Status

the interrupt.

The PCI 9080 PCI bus interrupt is level output. An

interrupt can be cleared by disabling an interrupt

enable bit or clearing the cause(s) of the interrupt.

3.10.1.1 Local Interrupt Input

Asserting Local bus input pin LINTi# can generate a PCI

bus interrupt. The PCI host processor can read the PCI

9080 Interrupt Control/Status Register to determine that

an interrupt is pending due to the LINTi# pin being

asserted.

The interrupt remains asserted as long as the LINTi# pin

is asserted and the Local Interrupt input is enabled.

Adapter specific action can be taken by the PCI host

processor to cause the local bus to release LINTi#.

3.10.1.2 Master/Target Abort Interrupt

The PCI 9080 sets the master abort or target abort

status bit in the PCI configuration register when it

detects a master or target abort. These status bits cause

PCI INTA# to be asserted if interrupts are enabled.

The interrupt remains asserted as long as the master or

target abort bits remain set in the PCI Configuration

Status Register and master/target abort interrupt is

enabled. Use a PCI Type 0 configuration access or a

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