LP3983S datasheet(6/8 Pages) POWER

6 / 8 page

LP3983S-06

May.-2017

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Page 6 of 8

Preliminary Datasheet

LP3983S

Applications Information

ike any low-dropout regulator, the external

capacitors used with the LP3983S must be carefully

selected for regulator stability and performance.

Using a capacitor whose value is >1µF on the

LP3983S input and the amount of capacitance can

be increased without limit. The input capacitor must

be located a distance of not more than 0.5 inch from

the input pin of the IC and returned to a clean analog

ground. Any good quality ceramic or tantalum can be

used for this capacitor. The capacitor with larger

value and lower ESR (equivalent series resistance)

provides better PSRR and line-transient response.

The output capacitor must meet both requirements

for minimum amount of capacitance and ESR in all

LDOs application. The LP3983S is designed

specifically to work with low ESR ceramic output

capacitor

space-saving

and

performance

consideration. Using a ceramic capacitor whose

value is at least 1µF with ESR is > 25mΩ on the

LP3983S output ensures stability. The LP3983S still

works well with output capacitor of other types due to

the wide stable ESR range. Output capacitor of

larger capacitance can reduce noise and improve

load transient response, stability, and PSRR. The

output capacitor should be located not more than 0.5

inch from the VOUT pin of the LP3983S and returned

to a clean analog ground.

Start-up Function Enable Function

The

LP3983S

features

LDO

regulator

enable/disable function. To assure the LDO regulator

will switch on, the EN turn on control level must be

greater than 1.4 volts. The LDO regulator will go into

the shutdown mode when the voltage on the EN pin

falls below 0.4 volts. For to protecting the system, the

LP3983S have a quick-discharge function. If the

enable function is not needed in a specific

application, it may be tied to VIN to keep the LDO

regulator in a continuously on state.

Feedback Capacitor

For adjustable version, connecting a 22pF between

output pin and FB pin significantly reduces output

voltage ripple, it is critical that the capacitor

connection should be direct and PCB traces should

be as short as possible.

The output voltage of LDO could be set by the

formula below:

Vout=VFB ×（1+R1/R2）

Considering the practical application, we may add a

small capacitor with R1 in parallel which could be

22pF or 47pF.

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