CLC417 datasheet(5/8 Pages) NSC

5 / 8 page

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Channel Matching

Channel matching and crosstalk efficiency are largely

dependent on board layout. The layout of National’s dual

amplifier evaluation boards are optimized to produce

maximum channel matching and isolation. Typical

channel matching for the CLC417 is shown in Figure 3.

Figure 3: Channel Matching

The CLC417’s channel-to-channel isolation is better than

70dB for input frequencies of 4MHz. Input referred

crosstalk vs. frequency is illustrated in Figure 4.

Figure 4: Input Referred Crosstalk vs. Frequency

Driving Cables and Capacitive Loads

When driving cables, double termination is used to

prevent reflections. For capacitive load applications, a

small series resistor at the output of the CLC417 will

improve stability.

The

Rs vs. Capacitive Load

plot, in the

Typical Performance section, gives the

recommended series resistance value for optimum

flatness at various capacitive loads.

Power Dissipation

The power dissipation of an amplifier can be described in

two conditions:

Quiescent Power Dissipation -

PQ (No Load Condition)

Total Power Dissipation -

PT (with Load Condition)

The following steps can be taken to determine the power

consumption for each CLC417 amplifier:

1. Determine the quiescent power

PQ = (VCC - VEE) • ICC

2. Determine the RMS power at the output stage

PO = (VCC - Vload) (Iload), where Vload and Iload

are the RMS voltage and current across the

external load.

3. Determine the total RMS power

PT = PQ + PO

Add the total RMS powers for both channels to determine

the power dissipated by the dual.

The maximum power that the package can dissipate at a

given temperature is illustrated in the

Power Derating

curves in the

Typical Performance section. The power

derating curve for any package can be derived by utiliz-

ing the following equation:

where: Tamb = Ambient temperature (°C)

JA = Thermal resistance, from junction to

ambient, for a given package (°C/W)

Layout Considerations

A proper printed circuit layout is essential for achieving

high

frequency

performance.

National

provides

evaluation boards for the CLC417 (CLC730038 - DIP,

CLC730036 - SOIC) and suggests their use as a guide

for high frequency layout and as an aid for device testing

and characterization.

Supply bypassing is required for best performance. The

bypass capacitors provide a low impedance return

current path at the supply pins. They also provide high

frequency filtering on the power supply traces.

Other

layout factors play a major role in high frequency

performance. The following are recommended as a basis

for high frequency layout:

1. Include 6.8

µF tantalum and 0.1µF ceramic

capacitors on both supplies.

2. Place the 6.8

µF capacitors within 0.75 inches

of the power pins.

3. Place the 0.1

µF capacitors less than 0.1

inches from the power pins.

4. Remove the ground plane near the input

and output pins to reduce parasitic

capacitance.

5. Minimize all trace lengths to reduce series

inductances.

Additional information is included in the evaluation board

literature.

Special Evaluation Board Considerations

To optimize off-isolation of the CLC417, cut the Rf trace

on both the 730038 and 730036 evaluation boards. This

cut minimizes capacitive feedthrough between the input

and

output.

Figure

indicates

the

alterations

recommended to improve off-isolation.

Frequency (MHz)

100

Av = +2

RL = 100Ω

Vo = 2Vpp

-450

-360

-270

-180

-90

Channel A

Channel B

Frequency (MHz)

-120

-100

-80

-60

-40

-20

100

(175

Tamb)

°−

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