Document Number: 64981

S11-0975-Rev. F, 16-May-11

www.vishay.com

5

Vishay Siliconix

SiC769

This document is subject to change without notice.

TIMING DEFINITIONS

Note:

GH is referenced to the high side source. GL is referenced to the low side source.

SiC769CD BLOCK DIAGRAM

Region

Definition

Symbol

1

Turn off propagation delay LS

2

Fall time LS

3

Dead time rising

4Rise time HS

5

Turn off propagation delay HS

6Fall time HS

7

Dead time falling

8

Rise time LS

PWM

GH

GL

SW

12 3 4

5 6

7

8

10 %

90 %

10 %

90 %

75 %

25 %

Figure 2

20K

BOOT

GH

VSWH

VDRV

GL

PGND

+

-

Vref = 1V

Vref = 1V

LG

+

-

Anti-Cross-

Conduction

Control Logic

VCIN

PWM Logic

Control &

State Machine

UVLO

PWM

VCIN

CGND

DSBL#

Thermal

Monitor &

Warning

THDN

SMOD#

VIN

Zero-Current

Dectect

+

-

VSWH

PGND

VDRV

UVLO

LG

GL

VSWH

PWM

DSBL#

Thermal Monitor

and Warning

PWM

Logic

Control

and State

Machine

SMOD#

VSWH

GH

BOOT

THDN

20K

Anti-

Cross-

Conduction

Control

Logic

Zero-

Current

Detect

-

+

-

+

-

+