SiC521 datasheet(9/16 Pages) VISHAY

9 / 16 page

SiC521, SiC521A

www.vishay.com

Vishay Siliconix

S15-0170-Rev. B, 09-Feb-15

Document Number: 62989

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Fig. 17 - ZCD_EN# Pull-Up Current vs. Temperature

Fig. 18 - Driver Quiescent Current vs. Temperature

PCB LAYOUT RECOMMENDATIONS

Step 1: VIN / PGND Planes and Decoupling

1. Layout VIN and PGND planes as shown above.

2. Ceramic capacitors should be placed directly between

VIN and PGND, and very close to the device for best

decoupling effect.

3. Different values / packages of ceramic capacitors should

be used to cover entire decoupling spectrum e.g. 1210,

0805, 0603, 0402.

4. Smaller capacitance values, placed closer to the devices,

VIN pin(s), results in better high frequency noise

absorbing.

Step 2: VSWH Plane

1. Connect output inductor to IC with large plane to lower

resistance.

2. VSWH plane also serves as a heat-sink for low-side

MOSFET. Make the plane wide and short to achieve the

best thermal path.

3. If

any

snubber

network

required,

place

the

components as shown above and the network can be

placed at bottom.

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

-9.0

-60

-40

-20

100 120 140

Temperature (°C)

ZCD_EN# = 0 V

270

290

310

330

350

370

390

410

430

-60

-40

-20

100 120 140

Temperature (°C)

PWM = FLOAT

VIN

VSWH

PGND

VIN Plane

PGND Plane

VSWH

Snubber

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