AM29DS163DB100WAF datasheet(12/50 Pages) AMD

12 / 50 page

Am29DS163D

ADV ANCE

I N FO RMAT I O N

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for tACC +

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

ICC4 in the “DC Characteristics” on page 33 represents

the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the

RESET# pin is driven low for at least a period of tRP,

the device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current is

greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the

RESET# pin returns to VIH.

Refer to “AC Characteristics” on page 36 for RESET#

parameters and to Figure 14, on page 37 for the timing

diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2. Am29DS163D Device Bank Divisions

Device

Part Number

Bank 1

Bank 2

Megabits

Sector Sizes

Megabits

Sector Sizes

Am29DS163D

4 Mbit

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

12 Mbit

Twenty-four

64 Kbyte/32 Kword

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