74LVC3G34 datasheet(2/14 Pages) PHILIPS

2 / 14 page

9397 750 14545

Product data sheet

Rev. 03 — 31 January 2005

2 of 14

Philips Semiconductors

74LVC3G34

Triple buffer gate

Quick reference data

[1]

CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(C

L × VCC

× f

o) = sum of outputs.

[2]

The condition is VI = GND to VCC.

Ordering information

Marking

Table 1:

Quick reference data

GND = 0 V; Tamb =25 °C.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

tPHL, tPLH propagation

delay input nA to

output nY

VCC = 1.8 V; CL = 30 pF; RL =1kΩ

3.8

VCC = 2.5 V; CL = 30 pF; RL = 500 Ω

2.4

VCC = 2.7 V; CL = 50 pF; RL = 500 Ω

2.5

VCC = 3.3 V; CL = 50 pF; RL = 500 Ω

2.2

VCC = 5.0 V; CL = 50 pF; RL = 500 Ω

1.9

input

capacitance

2.5

CPD

power

dissipation

capacitance per

gate

VCC = 3.3 V

[1] [2] -14

Table 2:

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC3G34DP

−40 °C to +125 °C

TSSOP8

plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm

SOT505-2

74LVC3G34DC

−40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74LVC3G34GT

−40 °C to +125 °C

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 1

× 1.95 × 0.5 mm

SOT833-1

Table 3:

Marking codes

Type number

Marking code

74LVC3G34DP

V34

74LVC3G34DC

Y34

74LVC3G34GT

Y34

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