STA003T datasheet(18/32 Pages) STMICROELECTRONICS

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DRA

Address: 0x48

Type: R/W

Software Reset: 0X00

Hardware Reset: 0X00

MSB

LSB

Description

DRA7

DRA6

DRA5

DRA4

DRA3

DRA2

DRA1

DRA0

OUTPUT ATTENUATION

000

0000

NO ATTENUATION

000

0000

-1dB

000

0001

-2dB

:::

::::

011

0000

-96dB

DRA register is used to attenuate the level of

audio output at the Right Channel using the but-

terfly shown in Fig. 11. When the register is set to

255

(0xFF),

the

maximum

attenuation

achieved.

A decimal unit correspond to an attenuation step

of 1 dB.

DRB

Address: 0x49

Type: R/W

Software Reset: 0xFF

Hardware Reset: 0xFF

MSB

LSB

Description

DRB7

DRB6

DRB5

DRB4

DRB3

DRB2

DRB1

DRB0

OUTPUT ATTENUATION

000

0000

NO ATTENUATION

000

0000

-1dB

000

0001

-2dB

:::

::::

011

0000

-96dB

DRB register is used to re-direct the Right Chan-

nel on the Left, or to mix both the Channels.

Default value is 0x00, corresponding at the maxi-

mum attenuation in the re-direction channel.

PCMDIVIDER

Address: 0x54

Type: RW

Software Reset: 0x01

Hardware Reset: 0x01

543

210

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PCMDIVIDER is used to set the frequency ratio

between the OCLK (Oversampling Clock for

DACs), and the SCKT (Serial Audio Transmitter

Clock).

The relation is the following:

SCKT_freq

OCLK_freq

(1 + PCMDIVIDER)

STA003T

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