5

TYPICAL SYSTEM OPERATION

The MSK4304RH is designed to be used with a +28 volt high voltage bus, +15 volt low power bus and +5 volt logic

signals. Proper derating should be applied when designing the MSK4304RH into a system. High frequency layout tech-

niques with ground planes on a printed circuit board is the only method that should be used for circuit construction. This will

prevent pulse jitter caused by excessive noise pickup on the current sense signal or the error amp signal.

Ground planes for the lower power circuitry and the high power circuitry should be kept separate. The connection

between the bottom of the current sense resistor, COM pin and the high power ground, AV-, BV- and CV- pins are

connected at this point. This is a critical path and high currents should not be flowing between the current sense and

COM. Inductance in this path should be kept to a minimum. An RC filter will filter out the current spikes and keep the

detected noise for those circuits down to a minimum.

In the system shown a PWM pulse by pulse current limit scheme controlled by the motor controller is implemented.

When controlling the motor speed by the PWM method, it is required that the low side switches be PWM pulsed to

ensure sufficient bootstrap capacitor charge to power the high side switch drives. The higher the PWM speed the

higher the current load on the drive supply.

8548-35 Rev. J 8/14