M48Z35-70PC6 datasheet(8/20 Pages) STMICROELECTRONICS

8 / 20 page

M48Z35, M48Z35Y

8/20

READ Mode

The M48Z35/Y is in the READ Mode whenever W

(WRITE Enable) is high, E (Chip Enable) is low.

The device architecture allows ripple-through ac-

cess of data from eight of 264,144 locations in the

static storage array. Thus, the unique address

specified by the 15 Address Inputs defines which

one of the 32,768 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

within Address Access time (tAVQV) after the last

address input signal is stable, providing that the E

and G access times are also satisfied. If the E and

G access times are not met, valid data will be

available after the latter of the Chip Enable Access

time (tELQV) or Output Enable Access time

(tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven to an

indeterminate state until tAVQV. If the Address In-

puts are changed while E and G remain active,

output data will remain valid for Output Data Hold

time (tAXQX) but will go indeterminate until the next

Address Access.

Figure 8. READ Mode AC Waveforms

Note: WRITE Enable (W)= High.

AI00925

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A14

DQ0-DQ7

VALID

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