522 - 05 - 02

11

GS1504 / GS1508 INTERFACING

Figures 30 through 34 show the artwork for a four layer

printed circuit evaluation board for the GS1504. The

schematic is shown in Fig 29. An FR-4 dielectric can be

used, however, controlled impedance transmission lines are

required for PCB traces longer than approximately 1cm.

Note the following PCB artwork features used to optimize

performance:

•

PCB trace width for HD rate signals is closely matched

to SMT component width to minimize reflections due to

change in trace impedance.

•

The

PCB

ground

plane

is

removed

under

the

GS1504/GS1508

input

components

to

minimize

parasitic capacitance.

•

The

PCB

ground

plane

is

removed

under

the

GS1504/GS1508

output

components

to

minimize

parasitic capacitance.

•

High speed traces are curved to minimize impedance

changes.

A picture of the GS1504/08 PCB assembly is shown in

Figure 34.

Fig. 29 GS1504/08 Evaluation Board Assembly

SDO

SDO

C11

4µ7

C12

4µ7

C11 AND C12 ARE

TC3216 TANTALUM

CAPACITORS.

L2

12n

75

1p

1p

75

12n

R9

C17

C18

R10

L3

J4

EDGEMNT_BNC

J5

EDGEMNT_BNC

C10

100n

R7

75

R8

75

C15

10n

SDO

SDO

GND

V

CC

SDI

SDI

V

EE

R

SET

1

2

3

4

8

7

6

5

U2

GS1508

R11

53.6

R8

75

R7

75

C16

1n

J1

CLOSE

TO

MUTE

C20

10n

C4

10n

CD/MUTE

VCC

VEE

SDO

SDO

VEE

nc

nc

CLI

VCC

VEE

SDI

SDI

VEE

MCLADJ

nc

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

C5

10n

TP3

CLI

C6

10n

R16

75

C7

47p

C8

47p

R15

37.5

L4 10n

R1

75

J2

VIDEO IN

R6

15k

R5

10k

R4

2k

1

2

J3

C1

1µ

C2

100n

C3

1n

TP1

TP2

GND

All resistors in ohms,

all capacitors in farads,

unless otherwise shown.