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CY7C1663KV18 bảng dữ liệu(PDF) 21 Page - Cypress Semiconductor

tên linh kiện CY7C1663KV18
Giải thích chi tiết về linh kiện  144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
PDF  31 Pages
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nhà sản xuất  CYPRESS [Cypress Semiconductor]
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CY7C1663KV18 bảng dữ liệu(HTML) 21 Page - Cypress Semiconductor

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Document Number: 001-44060 Rev. *O
Page 21 of 31
CY7C1663KV18/CY7C1665KV18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC applied to outputs in High Z ........ –0.5 V to VDDQ + 0.3 V
DC input voltage [22] ........................... –0.5 V to VDD + 0.3 V
Current into outputs (Low) .......................................... 20 mA
Static discharge voltage
(MIL-STD-883, M. 3015) ......................................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Range
Ambient
Temperature (TA)
VDD [23]
VDDQ [23]
Commercial
0 °C to +70 °C
1.8 ± 0.1 V
1.4 V to
VDD
Neutron Soft Error Immunity
Parameter
Description
Test
Conditions Typ Max* Unit
LSBU
Logical
Single-Bit
Upsets
25 °C
197
216
FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25 °C
0
0.01
FIT/
Mb
SEL
Single Event
Latch up
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical
2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [24]
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power supply voltage
1.7
1.8
1.9
V
VDDQ
I/O supply voltage
1.4
1.5
VDD
V
VOH
Output high voltage
Note 25
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VOL
Output low voltage
Note 26
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VOH(LOW)
Output high voltage
IOH =0.1 mA, Nominal impedance
VDDQ – 0.2
–
VDDQ
V
VOL(LOW)
Output low voltage
IOL = 0.1 mA, Nominal impedance
VSS
–
0.2
V
VIH
Input high voltage
VREF + 0.1
–
VDDQ + 0.15
V
VIL
Input low voltage
-0.15
–
VREF – 0.1
V
IX
Input leakage current
GND
 VI  VDDQ
2
–
2
A
IOZ
Output leakage current
GND
 VI  VDDQ, Output disabled
2
–
2
A
VREF
Input reference voltage [27] Typical Value = 0.75 V
0.68
0.75
0.95
V
Notes
22. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2).
23. Power up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
24. All voltage referenced to ground.
25. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175   RQ  350 .
26. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175   RQ  350 .
27. VREF(min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller.



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