2

PS8373D

08/03/99

PI74AVC16835

18-Bit Universal Bus Driver

w/3-State Outputs

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s

t

u

p

n

I

Y

s

t

u

p

t

u

O

E

OE

LK

L

CA

H

XXX

Z

LH

X

L

L

LH

X

H

H

LL

↑

LL

LL

↑

HH

LL

H

X

o

(

LLL

X

o

(

Pin Name

Description

OE

Output Enable Input (Active LOW)

LE

Latch Enable

CLK

Clock Input

A

Data Input

Y

Data Output

GND

Ground

Power

Product Pin Description

Note:

1

H = High Signal Level

L = Low Signal Level

Z = High Impedance

↑ = Transition LOW-to-HIGH

X = Irrelevant

2. Output level before the indicated steady-state input

conditions were established, provided that CLK is HIGH

before LE goes LOW.

3. Output level before the indicated steady-state input

conditions were established.

Logic Block Diagram

TO 17 OTHER CHANNELS

CLK

LE

A1

54

28

30

OE

27

1D

C1

CLK

Y1

3