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S70GL02GS bảng dữ liệu(PDF) 6 Page - Cypress Semiconductor

tên linh kiện S70GL02GS
Giải thích chi tiết về linh kiện  2 Gbit (256 MBytes), 3.0 V Flash Memory
PDF  19 Pages
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nhà sản xuất  CYPRESS [Cypress Semiconductor]
Trang chủ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S70GL02GS bảng dữ liệu(HTML) 6 Page - Cypress Semiconductor

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Document Number: 001-98296 Rev. *J
Page 6 of 19
S70GL02GS
2.
Input/Output Descriptions and Logic Symbol
Table 1 identifies the input and output package connections provided on the device.
Table 1. Input/Output Descriptions
Symbol
Type
Description
A26–A0
Input
Address lines for GL02GS.
DQ15–DQ0
I/O
Data input/output.
CE#
Input
Chip Enable.
OE#
Input
Output Enable.
WE#
Input
Write Enable.
VCC
Supply
Device Power Supply.
VIO
Supply
Versatile IO Input.
VSS
Supply
Ground.
RY/BY#
Output
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL, the
device is actively erasing or programming. At High Z, the device is in ready.
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#
Input
Write Protect/Acceleration Input. At VIL, disables program and erase functions in the outermost
sectors. At VHH, accelerates programming; automatically places device in unlock bypass mode.
Should be at VIH for all other conditions.
NC
No Connect
Not Connected. No device internal signal is connected to the package connector nor is there any
future plan to use the connector for a signal. The connection may safely be used for routing
space for a signal on a Printed Circuit Board (PCB).
DNU
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Cypress for test or other purposes and is not intended for connection
to any host system signal. Any DNU signal related function will be inactive when the signal is at
VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system
or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not
connect any host system signal to these connections.
RFU
No Connect
Reserved for Future Use. No device internal signal is currently connected to the package
connector but there is potential future use for the connector for a signal. It is recommended to not
use RFU connectors for PCB routing channels so that the PCB may take advantage of future
enhanced features in compatible footprint devices.



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