MB9B110T datasheet(2/133 Pages) CYPRESS

2 / 133 page

32-bit ARM

® Cortex®-M3

FM3 Microcontroller

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 002-04683 Rev.*C

Revised July 11, 2017

MB9B110T Series

The MB9B110T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive

cost.

These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as Motor

Control Timers, ADCs and Communication Interfaces (UART, CSIO, I

2C, LIN).

The products which are described in this data sheet are placed into TYPE2 product categories in "FM3 Family PERIPHERAL MANUAL".

Features

32-bit ARM Cortex-M3 Core

 Processor version: r2p1

 Up to 144 MHz Frequency Operation

 Memory Protection Unit (MPU): improves the reliability of

an embedded system

 Integrated Nested Vectored Interrupt Controller (NVIC): 1

NMI (non-maskable interrupt) and 48 peripheral interrupts

and 16 priority levels

 24-bit System timer (Sys Tick): System timer for OS task

management

On-chip Memories

[Flash memory]

 Up to 1 Mbyte

 Built-in Flash memory Accelerator System with 16 Kbyte

trace buffer memory

The read access to Flash memory can be achieved without

wait cycle up to the operation frequency of 72MHz. Even at

the operation frequency more than 72 MHz, an equivalent

access to Flash memory can be obtained by Flash memory

Accelerator System.

 Security function for code protection

[SRAM]

This Series on-chip SRAM is composed of two independent

SRAMs (SRAM0, SRAM1) . SRAM0 is connected to I-code

bus and D-code bus of Cortex-M3 core. SRAM1 is connected

to System bus.

 SRAM0: Up to 64 Kbytes.

 SRAM1: Up to 64 Kbytes.

External Bus Interface

 Supports SRAM, NOR and NAND Flash memory devices

 Up to 8 chips selected

 8-/16-bit Data width

 Up to 25-bit Address bit

 Maximum area size: Up to 256 Mbytes

 Supports Address/Data multiplex

 Supports external RDY function

Multi-function Serial Interface (Max 8 channels)

 4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4

channels without FIFO (ch.0 to ch.3)

 Operation mode is selectable from the followings for each

channel.



UART



CSIO



LIN



[UART]

 Full-duplex double buffer

 Selection with or without parity supported

 Built-in dedicated baud rate generator

 External clock available as a serial clock

 Hardware Flow control: Automatically controls the

transmission/reception with CTS/RTS (only for ch.4)

 Various error detection functions available (parity errors,

framing errors, and overrun errors)

[CSIO]

 Full-duplex double buffer

 Built-in dedicated baud rate generator

 Overrun error detection function available

[LIN]

 LIN protocol Rev.2.1 supported

 Full-duplex double buffer

 Master/Slave mode supported

 LIN break field generation (can be changed to 13-bit length

to 16-bit)

 LIN break delimiter generation (can be changed to 1-bit

length to 4-bit)

 Various error detection functions available (parity errors,

framing errors, and overrun errors)

2C]

Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)

supported

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