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CYUSB302X bảng dữ liệu(PDF) 1 Page - Cypress Semiconductor |
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CYUSB302X bảng dữ liệu(HTML) 1 Page - Cypress Semiconductor |
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1 / 34 page ![]() CYUSB302x SD3™ USB and Mass Storage Peripheral Controller Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-55190 Rev. *L Revised June 15, 2017 SD3™ USB and Mass Storage Peripheral Controller Features ■ Latest-generation storage support ❐ SD3.0/SDXC – UHS1 SDR50 / DDR50 Master ❐ eMMC 4.4 Master ❐ SDIO 3.0 Master ■ USB integration ❐ Certified USB 3.0 and USB 2.0 peripheral: SuperSpeed (SS), Hi-Speed (HS), and Full-Speed (FS) only) ❐ Thirty-two physical endpoints ❐ Integrated transceiver ❐ Accessory charger adaptor (ACA) support ■ Ultra low-power in core power-down mode ❐ Less than 60 µA with VBATT on and 20 µA with VBATT off ■ I2C master controller at 1 MHz ■ Selectable input clock frequencies ❐ 19.2, 26, 38.4, and 52 MHz ❐ 19.2-MHz crystal input support ■ Independent power domains for core and I/O ■ 10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package ■ 5.099 mm × 4.695 mm × 0.55 mm, with 0.4 mm pitch small footprint wafer-level chip scale package (WLCSP) Applications ■ USB thumb drives ■ Card readers ■ Laptop with SD slots ■ SD slot in TV/STB ■ WIFI Dongles ■ USB SDIO Bridge ■ Raid on-Chip Controller USB EPs GPIOs HS/FS Peripheral SS Peripheral SSTX- SSTX+ D+ D- SDIO/SD/MMC Controller S0-PORT S1-PORT I2C SSRX- SSRX+ FSLC[0] FSLC[1] FSLC[2] CLKIN CLKIN_32 XTALIN XTALOUT ARM926EJ-S JTAG Embedded SRAm (512 kB/ 256 KB) UART SPI I2S Logic Block Diagram Errata: For information on silicon errata, see “Errata” on page 30. Details include trigger conditions, devices affected, and proposed workaround. |
Số phần tương tự - CYUSB302X |
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Mô tả tương tự - CYUSB302X |
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