CCG3 datasheet(32/45 Pages) CYPRESS

32 / 45 page

EZ-PD™ CCG3

Document Number: 002-03288 Rev. *J

Page 32 of 45

Analog to Digital Converter

Table 32. ADC DC Specifications (Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SID.ADC.1

Resolution

ADC resolution

–

Bits

–

SID.ADC.2

INL

Integral non-linearity

–1.5

–

1.5

LSB

–

SID.ADC.3

DNL

Differential non-linearity

–2.5

–

2.5

LSB

–

SID.ADC.4

Gain Error

Gain error

–1

–

LSB

–

Table 33. ADC AC Specifications (Guaranteed by Design)

Spec ID

Parameter

Description

Min

Typ

Max Units

Details/Conditions

SID.ADC.5

SLEW_Max

Rate of change of sampled voltage

signal

––

V/ms

–

Table 34. VBUS_C Regulator DC Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SID.20vreg.1 VBUSREG

VBUS regulator output voltage

measured at VDDD for

VBUS = 4.5 V to 21.5 V

3–

3.6

VBUS = 4.5 V - 21.5 V range.

VDDD voltage measured with no

load and a load of 30 mA.

SID.20vreg.2 VBUSREG2

VBUS regulator output voltage

measured at VDDD for

VBUS = 3.5 V to 21.5 V

3–

3.6

VBUS = 4.5 V - 21.5 V range.

VDDD voltage measured with no

load and a load of 15 mA.

SID.20vreg.6 VBUSLINREG

VBUS regulator line regulation

for VBUS from 4.5 V to 21.5 V

––

0.5

%/V

VBUS supply varied from 4.5 V to

21.5 V and the change in the VDDD

measured.

Guaranteed by Characterization.

SID.20vreg.8 VBUSLOADREG VBUS regulator load regulation

for VBUS from 4.5 V to 21.5 V

––

0.2

%/mA

Supply of 4.5 V - 21.5 V applied on

VBUS and the load current swept

from 0 to 30 mA. The change in

VDDD is measured.

Guaranteed by Characterization.

Table 35. VBUS_C Regulator AC Specifications (Guaranteed by Characterization)

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

AC.20vreg.1 TSTART

Regulator Start-up time

–

120

µs

Apply VBUS and measure start time on

VDDD pin.

AC.20vreg.2 TSTOP

Regulator power down time

–

µs

Time from assertion of an internal disable

signal to for load current on VDDD to

decrease from 30 mA to 10 µA.

Table 36. VSYS Switch Specification

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

SID.vddsw.1 Res_sw

Resistance from VSYS supply

input to the output supply

VDDD

––

1.5

Ω

Measured with a load current of 5 mA - 10 mA

on VDDD.

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