SPMC802B datasheet(4/27 Pages) ETC

4 / 27 page

SPMC802B

3.1. CPU

The microprocessor of SPMC802B is a SUNPLUS high

performance processor equipped with Accumulator, Program

Counter, X Register, Y Register, Stack Pointer and Processor

Status Register (The same as 6502 instruction‘s structure).

SPMC802B is a fully static CMOS design.

The oscillation

frequency could be varied up to 6.0MHz depends on the

application needs.

3.1.1. Block diagram of Sunplus CPU

INSTRUCTION

PROCESSOR

STATUS

INSTRUCTION

DECODE

PCH

PCL

INPUT DATA

LATCH

IDLI

DATA BUS

BUFFER

INDEX

INTERRUPT

LOGIC

TIMING

CONTROL

CLOCK

GENERATOR

ACCUMULATOR

ALU

STACK POINT

RESET IRQ

NMI

CONTROL SECTION

A10

A11

A12

A13

A14

A15

ADDRESS

BUS

LEGEND

= 8BIT LINE

= 1 BIT LINE

CLK 0 IN

R/W

DATA

BUS

RDY

INDEX

3.2. Memory

3.2.1. Memory map

SPMC802B Supports 4.5K bytes of EPROM with 512 bytes test

ROM. It also has the configurable options can be programmed

by writer for different applications. The addresses for EPROM,

test ROM, and options are located in $0400h ~ $0FFFh and

$1800h ~ $1FFFh.

The RAM area is located in $0080h ~

$00FFh. The functional control registers and I/O control registers

are located in $0000h ~ $0013h.

A set of system control

registers can be configured through indexed access addresses

$003Eh and $003Fh. The buffers for stack pointer are started

from $01FFh with downward direction. This area is mirrored to

the RAM area $00FFh ~ $0080h.

A system control register

named Stack Limit Register (SLR) is used to limit the Stack area to

prevent the override of the normal operating contents in the RAM.

Once the Stack is over the limiter, CPU reset will be generated.

To prevent the illegal accesses on undefined addresses, there is a

qualification block to limit the accesses. The illegal accesses will

generate the CPU reset to restart the program.

3.2.2. NMI, Reset, IRQ vectors

The address of NMI (not provided in this chip), RESET and IRQ

are located from $1FFA to $1FFF. The interrupt vectors should

be specified in the program to have proper operation.

3.3. Oscillator

The SPMC802B supports AT-cut parallel resonant oscillated

Crystal /Resonator, or RC oscillator, or external clock sources by

configurable option (select one from those three types).

The

design

application

circuit

should

the

vendors‘ specifications or recommendations. The diagram listed

below

represents

typical

X’TAL/ROSC

circuits

for

most

applications:

SPMC802B

XO/R

20 pf

(a) Crystal or

Ceramic Resonator

Connections

SPMC802B

XO/R

VDD

Rosc

(b) RC Oscillator

Connections

Clock Source

Connections

SPMC802B

XO/R

UNCONNECTED

External Clock

Proprietary & Confidential

AUG. 07, 2002

Version: 1.0

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