2016-04-25

24

Version 1.2

SFH 7779

Interrupt function setting register (0x4Ah)

Setting of the interrupt functions.

R/W-Register 0x4A

Bit

7

6

5

4

3

2

1

0

PS INT

status

(read only)

ALS INT

status

(read only)

PS INT mode

INT assert

INT latch

INT trigger

0 inactive

00 PS_TH is only

active

0 INT „L“ is stable

0 INT is latched

00 inactive

0 inactive

0 inactive

00 PS_TH (PS high

threshold 0x4Bh &

0x4Ch) is only active

0 INT „L“ is stable if

newer measurement

results is also

interrupt active

0 INT is latched

until INT

register is read

or initialize

00 INT pin is

inactive

1 active

1active

01 PS_TH & PS_TL

(PS high & low

threshold) are active

as hysteresis

1 INT “L“ is de-assert

and re-assert if

newer measurement

results is also

interrupt active

1INT is updated

after each

measurement

01 triggered

by PS only

10 PS_TH & PS_TL

(PS high & low

threshold) are active

as outside detection

10 triggered

by ALS only

11 forbidden

11 triggered

by PS or ALS

PS INT and ALS INT status (bit <7;6>): Directly after reading the register the interrupt status for PS and

ALS and the INT Pin of the sensor is automatically set back to inactive status independent on the meas-

urement results.

PS INT mode (bit <5;4>): The INT modes are only valid for the PS interrupt function. For description

please see extra chapter „PS INT Modes“ (at the end of the register chapter).

INT assert (bit <3>): Is used to adjust the sensor behaviour to the used micro controller trigger settings.

In case a repeated trigger in low state is needed the

INT assert can be set to 1.

INT trigger (bit <2>): defines the source / sources for the interrupt.

INT latched (bit <1>): In latched mode the interrupt status stays active after the first activation. It is only

released by reading the status are performing an interrupt reset.

.

PS_TH_LSBs register (0x4Bh)

LSB for the PS threshold „HIGH“.

R/W-Register 0x4B

Bit

7

6

5

4

3

2

1

0

2

7

2

6

2

5

2

4

2

3

2

2

2

1

2

0

default

1

1

1

1

1

1

1

1