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HT48C06 bảng dữ liệu(PDF) 1 Page - Holtek Semiconductor Inc

tên linh kiện HT48C06
Giải thích chi tiết về linh kiện  Cost-Effective I/O Type 8-Bit MCU
PDF  38 Pages
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nhà sản xuất  HOLTEK [Holtek Semiconductor Inc]
Trang chủ  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT48C06 bảng dữ liệu(HTML) 1 Page - Holtek Semiconductor Inc

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HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Cost-Effective I/O Type 8-Bit MCU
Block Diagram
Rev. 1.10
1
June 9, 2004
General Description
The HT48R05A-1/HT48C05 and HT48R06A-1/
HT48C06 are 8-bit high performance, RISC architec-
ture microcontroller devices specifically designed for
cost-effective multiple I/O control product applications.
The mask version HT48C05 and HT48C06 are fully pin
and functionally compatible with the OTP version
HT48R05A-1 and HT48R06A-1 devices.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 13 bidirectional I/O lines
· An interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with over-
flow interrupt and 8-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· Program memory ROM:
512
´14 for HT48R05A-1/HT48C05
1024
´14 for HT48R06A-1/HT48C06
· Data memory RAM
32
´8 for HT48R05A-1/HT48C05
64
´8 for HT48R06A-1/HT48C06
· Buzzer driving pair and PFD supported
· HALT function and wake-up feature reduce power
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· Allinstructionsinoneortwomachinecycles
· 14-bit table read instruction
· Two-level subroutine nesting
· Bit manipulation instruction
· Powerful instructions:
62 for HT48R05A-1/HT48C05
63 for HT48R06A-1/HT48C06
· Low voltage reset function
· 16-pin SSOP package
18-pin DIP/SOP package
I N T / P C 0
O S C 2
O S C 1
R E S
V D D
M U X
P A C
P A
P O R T A
P A 0 ~ P A 7
f S Y S / 4
W D T S
W D T
P C C
P C
P O R T C
P C 0 ~ P C 1
P B C
P B
P O R T B
P B 0 ~ P B 2
V S S
B Z / B Z
P C 0
P r o g r a m
R O M
P r o g r a m
C o u n t e r
I n t e r r u p t
C i r c u i t
S T A C K 0
S T A C K 1
I N T C
D A T A
M e m o r y
I n s t r u c t i o n
R e g i s t e r
M
U
X
I n s t r u c t i o n
D e c o d e r
S T A T U S
A L U
S h i f t e r
T i m i n g
G e n e r a t o r
A C C
R C O S C
W D T P r e s c a l e r
M
U
X
M P
T M R / P C 1
T M R
T M R C
P r e s c a l e r
f S Y S
P C 1
M
U
X


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