CYRF9935

Document Number: 001-88748 Rev. *G

Page 21 of 47

RX FIFO Access

We can access RX FIFO with SPI command, R_RX_PAYLOAD. We use the SPI command to read data from RX FIFO while IRQ is

asserted and RX_DR status bit is set. In CYRF9935, RXer will not receive the packets when RX FIFO is full.

SPI Command

SPI Timing

In general, a SPI Command consists of a command and data part in that order. The command part is used to represent the purpose

of the SPI command. For example, in Figure 8, C7–C0 is the command part. D0, D1, D2, and so on are defined as the data part.

Figure 8. SPI Read Timing

Figure 9. SPI Write Timing

Figure 10. SPI Timing Requirement

SPI_nSS

SCK

MOSI

MISO

SPI_nSS

SCK

MOSI

MISO

SPI_SS

CLK

MOSI

MISO