2004 Mar 22

11

Philips Semiconductors

Product specification

Quad 2-input NAND gate (open drain)

74LVC38A

UNIT

(1)

QZ

y

w

v

θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

mm

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

0.65

6.6

6.2

0.4

0.3

0.72

0.38

8

0

o

o

0.13

0.1

0.2

1

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1

MO-153

99-12-27

03-02-18

D

Z

e

0.25

17

14

8

θ

A

Q

detail X

L

(A )

3

E

c

X

A

y

0

2.5

5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

A

max.

1.1

pin 1 index