74HC164N datasheet(13/24 Pages) PHILIPS

13 / 24 page

9397 750 14693

Product data sheet

Rev. 03 — 4 April 2005

13 of 24

Philips Semiconductors

74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

Table 10:

Dynamic characteristics for 74HCT164

GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise speciﬁed

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Tamb = 25 °C

tPHL, tPLH propagation delay

CP to Qn

VCC = 4.5 V;

see Figure 7

1736ns

tPHL

propagation delay

MR to Qn

VCC = 4.5 V;

see Figure 8

1938ns

tTHL, tTLH output transition time

VCC = 4.5 V;

see Figure 7

clock pulse width;

HIGH or LOW

VCC = 4.5 V;

see Figure 7

master reset pulse width;

LOW

VCC = 4.5 V;

see Figure 8

trem

removal time MR to CP

VCC = 4.5 V;

see Figure 8

tsu

set-up time

DSA, and DSB to CP

VCC = 4.5 V;

see Figure 9

hold time DSA, and DSB

to CP

VCC = 4.5 V;

see Figure 9

−2-

fmax

maximum clock pulse

frequency

VCC = 4.5 V;

see Figure 7

MHz

Tamb = −40 °C to +85 °C

tPHL, tPLH propagation delay

CP to Qn

VCC = 4.5 V;

see Figure 7

--45

tPHL

propagation delay

MR to Qn

VCC = 4.5 V;

see Figure 8

--48

tTHL, tTLH output transition time

VCC = 4.5 V;

see Figure 7

--19

clock pulse width;

HIGH or LOW

VCC = 4.5 V;

see Figure 7

--ns

master reset pulse width;

LOW

VCC = 4.5 V;

see Figure 8

--ns

trem

removal time MR to CP

VCC = 4.5 V;

see Figure 8

--ns

tsu

set-up time

DSA, and DSB to CP

VCC = 4.5 V;

see Figure 9

--ns

hold time DSA, and DSB

to CP

VCC = 4.5 V;

see Figure 9

--ns

fmax

maximum clock pulse

frequency

VCC = 4.5 V;

see Figure 7

MHz

Tamb = −40 °C to +125 °C

tPHL, tPLH propagation delay

CP to Qn

VCC = 4.5 V;

see Figure 7

--54

tPHL

propagation delay

MR to Qn

VCC = 4.5 V;

see Figure 8

--57

tTHL, tTLH output transition time

VCC = 4.5 V;

see Figure 7

--22

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